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Xilinx KC724 IBERT Getting Started Manual

Xilinx KC724 IBERT Getting Started Manual

(ise design suite 14.3)
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KC724 IBERT
Getting Started Guide
(ISE Design Suite 14.3)
UG930 (v1.0) October 23, 2012
This document applies to the following software versions: ISE Design Suite 14.3 and 14.4
This document applies to the following software versions: ISE Design Suite 14.3 and 14.4
This document applies to the following software versions: ISE Design Suite 14.3 and 14.4
This document applies to the following software versions: ISE Design Suite 14.3 and 14.4

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  • Page 1 KC724 IBERT Getting Started Guide (ISE Design Suite 14.3) UG930 (v1.0) October 23, 2012 This document applies to the following software versions: ISE Design Suite 14.3 and 14.4 This document applies to the following software versions: ISE Design Suite 14.3 and 14.4 This document applies to the following software versions: ISE Design Suite 14.3 and 14.4...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 3 ............. 2 Chapter 1: KC724 IBERT Getting Started Guide Overview .
  • Page 4 KC724 IBERT Getting Started Guide UG930 (v1.0) October 23, 2012...

  • Page 5: Overview

    Overview Chapter 1 KC724 IBERT Getting Started Guide Overview This document provides a procedure for setting up the KC724 Kintex™-7 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using the ISE Design Suite. The designs that are required to run the IBERT demonstration are stored in a Secure Digital (SD) memory card that is provided with the KC724 board.

  • Page 6: Requirements

    • Xilinx ISE® Design Suite version 14.3 or higher • PC with a version of the Windows operating system supported by Xilinx ISE Design Suite Setting Up the KC724 Board This section describes how to set up the KC724 board.

  • Page 7: Extracting The Project Files

    GTX transceiver Quads 115, 116, 117, and 118 on the KC724 board. Note: Figure 1-1 is for reference only and might not reflect the current revision of the board. KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...
  • Page 8 Chapter 1: KC724 IBERT Getting Started Guide X-Ref Target - Figure 1-1 QUAD_116 QUAD_117 QUAD_115 QUAD_118 UG930_c1_01_061412 Figure 1-1: GTX Quad Locations All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector pad which interfaces with Samtec BullsEye connectors.

  • Page 9: Attach The Gtx Quad Connector

    Attach the GTX Quad Connector Before connecting the BullsEye cable assembly to the board, firmly secure the blue elastomer seal provided with the cable assembly to the bottom of the connector housing if KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...

  • Page 10: Gtx Transceiver Clock Connections

    Chapter 1: KC724 IBERT Getting Started Guide it isn't already inserted (see Figure 1-4). Note: Figure 1-4 is for reference only and might not reflect the current version of the connector. X-Ref Target - Figure 1-4 UG930_c1_04_101112 Figure 1-4: BullsEye Connector with Elastomer Seal...

  • Page 11: Gtx Tx/Rx Loopback Connections

    X-Ref Target - Figure 1-6 UG930_c1_06_101112 Figure 1-6: SMA F-F Adapter X-Ref Target - Figure 1-7 TX Coax SMA F-F Adapter RX Coax UG930_c1_07_101112 Figure 1-7: TX-To-RX Loopback Connection Example KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...

  • Page 12: Configuring The Fpga

    Chapter 1: KC724 IBERT Getting Started Guide Figure 1-8 shows the KC724 board with the cable connections required for the Quad 115 GTX IBERT demonstration. X-Ref Target - Figure 1-8 CKOUT1_N CKOUT1_P QUAD_115 TX/RX Loopback Connections UG930_c1_08_081412 Figure 1-8: Cable Connections for Quad 115 GTX IBERT Demonstration...

  • Page 13: Setting Up The Chipscope Pro Software

    The .cpj file loads pre-saved project settings for the demonstration including MGT/IBERT and clock module control parameters. For more information regarding MGT/IBERT settings, refer to UG029, ChipScope Pro Software Cores. KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...

  • Page 14: Starting The Superclock-2 Module

    Chapter 1: KC724 IBERT Getting Started Guide Click the Open Cable button (Figure 1-10). X-Ref Target - Figure 1-10 Open Cable Button UG930_c1_10_101112 Figure 1-10: Open Cable Button When the dialog appears asking to set up the core with the settings from the current...
  • Page 15 X-Ref Target - Figure 1-13 The ROM address value for the Si5368 clock multiplier is preset to 19 (125.000 MHz) Si5368 start button UG930_c1_13_101112 Figure 1-13: Si5368 Address, Frequency and Start Button KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...

  • Page 16: Viewing Gtx Transceiver Operation

    Chapter 1: KC724 IBERT Getting Started Guide In the project panel, click IBERT Console (Figure 1-14) to view GTX transceiver operation. X-Ref Target - Figure 1-14 UG930_c1_14_101112 Figure 1-14: Project Panel - IBERT Console (GTX) Viewing GTX Transceiver Operation After completing...

  • Page 17: In Case Of Rx Bit Errors

    Figure 1-16: Click BERT Reset Button to Zero a Non-Zero RX Error Count If the MGT Link Status shows No Link for one or more transceivers click the respective TX Reset button followed by BERT Reset (Figure 1-17). KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...

  • Page 18: Closing The Ibert Demonstration

    Chapter 1: KC724 IBERT Getting Started Guide X-Ref Target - Figure 1-17 ug930_c1_17_101512 Figure 1-17: Click TX Reset then BERT Reset If MGT Link Status = No Link Closing the IBERT Demonstration To stop the IBERT demonstration: Close the ChipScope application by selecting File → Exit.

  • Page 19: Superclock-2 Frequency Table

    Interlaken 265.625 594.000 Generic 275.000 Interlaken 390.625 SMPTE435M 167.063 Generic 280.000 Interlaken 531.250 SMPTE435M 334.125 Generic 285.000 OBSAI 76.800 SMPTE435M 668.250 Generic 290.000 OBSAI 153.600 XAUI 78.125 Generic 295.000 KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...

  • Page 20: Creating The Gtx Ibert Core

    Chapter 1: KC724 IBERT Getting Started Guide Table 1-2: Si570 and Si5368 Frequency Table (Cont’d) Frequency Frequency Frequency Address Protocol Address Protocol Address Protocol (MHz) (MHz) (MHz) Generic 300.000 Generic 365.000 Generic 430.000 Generic 305.000 Generic 370.000 Generic 435.000 Generic 310.000...
  • Page 21 Speed Grade: -3 Figure 1-19 shows the correct settings. X-Ref Target - Figure 1-19 UG930_c1_19_101112 Figure 1-19: CORE Generator Project Options (Part Options) Click OK to close the Project Options window. KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...
  • Page 22 Chapter 1: KC724 IBERT Getting Started Guide In the IP Catalog pane of the CORE Generator window (Figure 1-20) select: Debug & Verification → Debug → IBERT 7 Series GTX (ChipScope Pro - IBERT) 2.02.a X-Ref Target - Figure 1-20...

  • Page 23: Quad

    Enter the information shown here and in Figure 1-22, then click Next: • No. of Quads: 1 • Select Quad: QUAD 115 • Max Rate (Gbps): 12.5 • Refclk (MHz): 125.000 • GT count: 4 KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...
  • Page 24 Chapter 1: KC724 IBERT Getting Started Guide X-Ref Target - Figure 1-22 UG930_c1_22_101112 Figure 1-22: CORE Generator - IBERT GTX Customization - Page 2 10. Enter the information shown here and in Figure 1-23, then click Next: • MGT0_115: CUSTOM1 / 12.5 Gbps •...
  • Page 25 11. Enter the information shown here and in Figure 1-24, then click Next: • MGT0_115: MGTREFCLK1 115 • MGT1_115: MGTREFCLK1 115 • MGT2_115: MGTREFCLK1 115 • MGT3_115: MGTREFCLK1 115 KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...
  • Page 26 Chapter 1: KC724 IBERT Getting Started Guide X-Ref Target - Figure 1-24 UG930_c1_24_101112 Figure 1-24: CORE Generator - IBERT GTX Customization - Page 5 12. Verify the information shown in Figure 1-25, then click Generate. X-Ref Target - Figure 1-25...
  • Page 27 13. The generation process will take a few minutes. When complete, a Readme window will appear (Figure 1-26). X-Ref Target - Figure 1-26 UG930_c1_26_101112 Figure 1-26: CORE Generator - Readme KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012...
  • Page 28 Chapter 1: KC724 IBERT Getting Started Guide www.xilinx.com KC724 IBERT Getting Started Guide UG930 (v1.0) October 23, 2012...
  • Page 29 For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products. The availability of replacement products is subject to product discontinuation policies at Xilinx.
  • Page 30 Appendix A: Warranty www.xilinx.com KC724 IBERT Getting Started Guide UG930 (v1.0) October 23, 2012...

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