Xilinx 7 Series User Manual page 147

5.
Serial Clock Divider
Each transmitter PMA module has a D divider that divides down the clock from the PLL for lower
line rate support. This serial clock divider, D, can be set statically for applications with a fixed line
rate or it can be changed dynamically for protocols with multiple line rates. The control for the serial
divider is described in
7 series FPGAs documentation page
To use the D divider in fixed line rate applications, the RXOUT_DIV attribute must be set to the
appropriate value, and the RXRATE port needs to be tied to 3'b000. Refer to the Static Setting via
Attribute column in
To use the D divider in multiple line rate applications, the RXRATE port is used to dynamically
select the D divider value. The RXOUT_DIV attribute and the RXRATE port must select the same
D divider value upon device configuration. After device configuration, the RXRATE is used to
dynamically change the D divider value. Refer to the Dynamic Control via Ports column in
Table 4-16
Table 4-16: RX PLL Output Divider Setting
D Divider Value
Parallel Clock Divider and Selector
The parallel clock outputs from the RX clock divider control block can be used as a fabric logic
clock depending on the line rate and protocol requirements.
The recommended clock for the FPGA logic is the RXOUTCLK from one of the GTP transceivers.
It is also possible to bring the MGTREFCLK directly to the fabric and use as the fabric clock.
RXOUTCLK is preferred for general applications because it has an output delay control used for
applications that bypass the RX buffer for constant datapath delay. Refer to
page 174
The RXOUTCLKSEL port controls the input selector and allows these clocks to be output via
RXOUTCLK port:
•
•
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
For details about placement constraints and restrictions on clocking resources (MMCME2,
PLLE2, IBUFDS_GTE2, BUFG, etc.), refer to UG472, 7 Series FPGAs Clocking Resources
User Guide.
Table 4-16. For details about the line rate range per speed grade, refer to the
Table 4-16 for details.
for details.
Static Setting via Attribute
RXOUT_DIV = 1
1
RXRATE = 3'b000
RXOUT_DIV = 2
2
RXRATE = 3'b000
RXOUT_DIV = 4
4
RXRATE = 3'b000
RXOUT_DIV = 8
8
RXRATE = 3'b000
for more details.
RXOUTCLKSEL = 3'b001: RXOUTCLKPCS path is not recommended to be used as it
incurs extra delay from the PCS block.
RXOUTCLKSEL = 3'b010: RXOUTCLKPMA is the recovered clock that can be brought
out to the FPGA logic. The recovered clock is used by protocols that do not have a clock
compensation mechanism and require to use a clock synchronous to the data (the recovered
www.xilinx.com
RX Fabric Clock Output Control
for the appropriate data sheet.
Dynamic Control via Ports
RXOUT_DIV = Ignored
RXRATE = 3'b001
RXOUT_DIV = Ignored
RXRATE = 3'b010
RXOUT_DIV = Ignored
RXRATE = 3'b011
RXOUT_DIV = Ignored
RXRATE = 3'b100
RX Buffer Bypass,
147
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