Tx Phase Interpolator Ppm Controller - Xilinx 7 Series User Manual

Table 3-24: TX Fabric Clock Output Control Ports (Cont'd)
TXDLYBYPASS
TXRATEMODE
Table 3-25
Table 3-25: TX Fabric Clock Output Control Attributes
TRANS_TIME_RATE
TXBUF_RESET_ON_RATE_C
HANGE
TXOUT_DIV

TX Phase Interpolator PPM Controller

Functional Description
The TX Phase Interpolator Parts Per Million (TXPIPPM) Controller module provides support for
dynamically controlling the TX phase interpolator (TX PI). Located in the TX PCS, its inputs come
from the FPGA TX Interface and it outputs to the TX PMA. Applications exist that require fine-tune
control of the data in the TX PMA. Control of the output clock from the PLL is achieved through a
TX PI, which in turn can be controlled by the TX phase interpolator PPM controller module. The
FPGA logic can control the TX PI in the TX PMA through the use of the TX phase interpolator PPM
controller module in the PCS.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Port Dir Clock Domain
In
In
defines the attributes required for TX fabric clock output control.
Attribute Type
8-bit Hex
String
Integer
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TX Phase Interpolator PPM Controller
Async TX delay alignment bypass:
0: Uses the TX delay alignment circuit.
Set to 1'b0 when the TX buffer is
bypassed.
1: Bypasses the TX delay alignment
circuit. Set to 1'b1 when the TX buffer
is used.
Async Determines if TXRATE should be treated as
synchronous or asynchronous.
0: Synchronous. When set to 1'b0, an
automatic reset sequence occurs in
response to a change on the TXRATE
port.
1: Asynchronous.
Description
Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used. This attribute determines when PHYSTATUS
and TXRATEDONE are asserted after a rate
change.
When set to TRUE, this attribute enables an
automatic TX buffer reset during a rate change
event initiated by a change in TXRATE.
This attribute controls the setting for the TX serial
clock divider. This attribute is only valid when
TXRATE = 3'b000. Otherwise the D divider
value is controlled by TXRATE. Valid settings are
1, 2, 4, and 8.
Description
111
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