Xilinx 7 Series User Manual page 165

Figure 4-32
PMA before and after the data shift. In this mode, the data is shifted right by one bit for every
RXSLIDE pulse issued, but there is some intermediate data with the bits shifted left before the final
data appears on the bus. When RXSLIDE_MODE = PMA is used, the RX recovered clock phase is
shifted by 2 UI for every alternate RXSLIDE pulse.
X-Ref Target - Figure 4-32
RXUSRCLK2
RXSLIDE
RXDATA 00000000000010011111
TXDATA
Figure 4-32: Manual Data Alignment Using RXSLIDE for RX_DATA_WIDTH = 20 Bits and
Note relevant to
1.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the waveforms for manual alignment using RXSLIDE in RXSLIDE_MODE =
A minimum of 32 RXUSRCLK2
cycles are required between two
Intermediate Data
0000000000
0100111110
00000000001001111100
RXSLIDE_MODE = PMA
Figure 4-32:
Latency between the slide and the slide result at RXDATA depends on the number of active RX
PCS blocks in the datapath.
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RX Byte and Word Alignment
RXSLIDE pulses
Slide results on RXDATA
after several cycles of latency
through the PCS path
10000000000001001111 11000000000000100111
UG482_c4_21_111011
165
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