Gtx Transceivers And Reference Clocks - Xilinx Virtex-7 VC7203 User Manual

Chapter 1: VC7203 Board Features and Operation

GTX Transceivers and Reference Clocks

Callout 4,
The VC7203 board provides access to all GTX transceiver and reference clock pins on the
FPGA as shown in
RX-TX lanes. Four lanes are referred to as a Quad.
Note:
Note:
X-Ref Target - Figure 1-10
QUAD_112
QUAD_111
Each GTX Quad and its associated reference clocks (CLK0 and CLK1) are brought out to a
connector pad which interfaces with Samtec BullsEye connectors used with the Samtec
HDR-155805-01-BEYE cable assembly. Contact Samtec, Inc. for information about this or
other cable assemblies.
connector pinout.
22
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Figure 1-2.
Figure 1-10. The GTX transceivers are grouped into nine sets of four
QUAD 111 and QUAD 112 do not connect to pins on the XCVX485T.
Figure 1-10 is for reference only and might not reflect the current revision of the board.
QUAD_115
QUAD_114
QUAD_113
Figure 1-10: GTX Quad Locations
Figure 1-11
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QUAD_116
QUAD_117
QUAD_118
QUAD_119
A shows the connector pad.
VC7203 GTX Transceiver Characterization Board
UG957_c1_10_121613
Figure 1-11 B shows the
UG957 (v1.3) October 17, 2014