Xilinx 7 Series User Manual page 15

Figure 1-3
X-Ref Target - Figure 1-3
TX TX
TX
OOB Pre/
Driver
and Post
PCIe Emp
TX Clock
PISO
Dividers
TX Phase
Interpolator
TX-PMA
Clock From PLL0 or PLL1
Clock From PLL0 or PLL1
RX Clock
Dividers
RX EQ
RX OOB
SIPO
Refer to
clocks to the RX and TX clock dividers.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
illustrates the topology of a GTPE2_CHANNEL primitive.
PCIe
Beacon
SATA
OOB
Polarity
To RX Parallel
Data (Near-End
PCS Loopback)
PRBS
Checker
Polarity
Figure 1-3: GTPE2_CHANNEL Primitive Topology
Figure 2-9, page 35 for the description of the channel clocking architecture, which provides
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Gearbox
Pattern
Generator
Phase
Adjust
FIFO
8B/10B
Encoder
From RX Parallel Data
(Far-End PMA Loopback)
Comma
Detect
And
RX PIPE Control
Align
RX Status Control
RX
Elastic
Buffer
8B/10B
Decoder
Overview and Features
TX
TX PIPE
Control
FPGA
TX
Interface
TX Phase
Interpolator
Controller
TX-PCS
From RX Parallel Data
(Far-End PCS Loopback)
FPGA
RX
Interface
RX
Gearbox
UG482_c1_03_110811
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