Xilinx 7 Series User Manual page 303

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
009C
5:0
(Cont'd)
15:12
009D
11:8
009D
7
009D
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W RXBUF_THRESH_UNDFLW
R/W RXBUF_EIDLE_HI_CNT
R/W RXBUF_EIDLE_LO_CNT
R/W RXBUF_ADDR_MODE
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Attribute Attribute
Bits Encoding
36
37
38
39
40
41
42
43
44
45
46
47
48
49
5:0
50
51
52
53
54
55
56
57
58
59
60
61
62
63
3:0 0-15
3:0 0-15
FULL
0
FAST
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DRP
Encoding
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0-15
0-15
0
1
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