Xilinx 7 Series User Manual page 167

Table 4-25: RX Byte and Word Alignment Ports (Cont'd)
Port Name
RXSLIDE
Table 4-26
Table 4-26: RX Byte and Word Alignment Attributes
Attribute
ALIGN_COMMA_WORD
ALIGN_COMMA_ENABLE
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Dir Clock Domain
In RXUSRCLK2 RXSLIDE implements a comma alignment bump control. When
RXSLIDE is asserted, the byte alignment is adjusted by one bit, which
permits determination and control of byte alignment by the FPGA logic.
Each assertion of RXSLIDE causes just one adjustment.
RXSLIDE must be deasserted for more than 32 RXUSRCLK2 cycles
before it can be reasserted to cause another adjustment.
When asserted, RXSLIDE takes precedence over normal comma
alignment.
For proper operation, the user should set these values:
defines the RX byte and word alignment attributes.
Type
Integer This attribute controls the alignment of detected commas within a multi-byte
datapath.
1: Align comma to either of the 2 bytes for a 2-byte interface, any of the 4
bytes for a 4-byte interface.
The comma can be aligned to either the even bytes or the odd bytes of
RXDATA output.
2: Align comma to the even bytes only. The aligned comma is guaranteed to
be aligned to even bytes RXDATA[9:0] for a 2-byte interface,
RXDATA[9:0]/RXDATA[29:20] for a 4-byte interface.
Refer to
the different ALIGN_COMMA_WORD and RX_DATA_WIDTH settings.
Protocols that send commas in even and odd positions must set
ALIGN_COMMA_WORD to 1.
10-bit Binary Sets which bits in MCOMMA/PCOMMA must be matched to incoming data
and which bits can be of any value.
This attribute is a 10-bit mask with a default value of 1111111111. Any bit in
the mask that is reset to 0 effectively turns the corresponding bit in MCOMMA
or PCOMMA to a don't care bit.
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Description
RXPCOMMAALIGNEN = 0;
RXMCOMMAALIGNEN = 0;
RXCOMMADETEN = 1;
SHOW_REALIGN_COMMA = FALSE
Description
Figure 4-30, page 164 for comma alignment boundaries allowed for
RX Byte and Word Alignment
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