Rx Fabric Clock Output Control - Xilinx 7 Series User Manual

Chapter 4: Receiver

RX Fabric Clock Output Control

Functional Description
The RX clock divider control block has two main components: serial clock divider control and
parallel clock divider and selector control. The clock divider and selector details are illustrated in
Figure
X-Ref Target - Figure 4-18
RXP/N
PLL0OUTCLK
PLL1OUTCLK
PLL0 PLL1
REFCLK Sel REFCLK Sel
GTPE2_
COMMON
REFCLK Distribution
IBUFDS_GTE2
MGTREFCLK[0/1]P
MGTREFCLK[0/1]N
Note relevant to
1.
2.
3.
4.
146
Send Feedback
4-18.
RX PMA
RXDATA
SIPO
CDR
/D
/4 or
/2
{1,2,4,8} /5
RXSYSCLKSEL[0]
0 1
PLL0REFCLK
0
PLL1REFCLK
1
RXSYSCLKSEL[1]
GTPE2_CHANNEL (GTP Transceiver Primitive)
O
0
ODIV2
/2 1
REFCLK_CTRL 2
Figure 4-18: RX Serial and Parallel Clock Divider
Figure 4-18:
RXOUTCLKPCS and RXOUTCLKFABRIC are redundant outputs. RXOUTCLK should be
used for new designs.
The REFCLK_CTRL option is controlled automatically by software and is not user selectable.
The user can only route one of IBUFDS_GTE2's O or ODIV2 outputs to the FPGA logic.
IBUFDS_GTE2 is a redundant output for additional clocking scheme flexibility.
The selection of the /4 or /5 divider block is controlled by the RX_DATA_WIDTH attribute
from the GTPE2_CHANNEL primitive. /4 is selected when RX_DATA_WIDTH = 16 or 32. /5
is selected when RX_DATA_WIDTH = 20 or 40.
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RX PCS
RX Polarity
Control
'1'
000
RXOUTCLKPCS
001
RXOUTCLKPMA
010
RXPLLREFCLK_DIV1
011
RXPLLREFCLK_DIV2
/2 100
RXOUTCLKSEL
7 Series FPGAs GTP Transceivers User Guide
RXDATA to
Downstream
PCS Blocks
RXOUTCLKPCS 1
Delay
0
Aligner
RXOUTCLK
1
RXDLYBYPASS
RXOUTCLKFABRIC 1
IBUFDS_GTE2 Output to Logic 3
UG482_C4_10_021113
UG482 (v1.9) December 19, 2016