Xilinx 7 Series User Manual page 291

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0045
15:10
(Cont'd)
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W CLK_COR_MAX_LAT
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Attribute Attribute
Bits Encoding
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
5:0 24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
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DRP
Encoding
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
291