Xilinx 7 Series User Manual page 87

Table 3-9
Table 3-9: TX Gearbox Attributes
GEARBOX_MODE
TXGEARBOX_EN
Enabling the TX Gearbox
To enable the TX gearbox for the GTP transceiver, set the attribute TXGEARBOX_EN to TRUE.
The GEARBOX_MODE attribute controls the GTP transceiver's TX and RX gearbox use modes.
TX Gearbox Bit and Byte Ordering
Figure 3-7
64B/66B encoding when using a 2-byte logic interface (TX_DATA_WIDTH = 16 (2-byte)). The
input consists of a 2-bit header and 16 bits of data. On the first cycle, the header and 14 bits of data
exit the TX gearbox. On the second cycle, the remaining two data bits from the previous cycle's
TXDATA input along with 14 data bits from the current TXDATA input exit the TX gearbox. This
continues for the third and fourth cycle. On the fifth cycle, the output of the TX gearbox contains
two remaining data bits from the first 66-bit block, the header of the second 66-bit block, and 28 data
bits from the second 66-bit block.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
defines the TX gearbox attributes.
Attribute Type
3-bit Binary
String
shows an example of the first four cycles of data entering and exiting the TX gearbox for
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Description
This attribute indicates the TX and RX gearbox modes:
• Bit 2: Set to 0. Unused.
• Bit 1: Set to 0.
0: Use the external sequence counter and apply inputs
to TXSEQUENCE.
1: Not supported.
• Bit 0:
0: 64B/67B gearbox mode for Interlaken.
1: 64B/66B gearbox.
When TRUE, this attribute enables the TX gearbox.
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TX Gearbox
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