Xilinx 7 Series User Manual page 102

Chapter 3: Transmitter
Figure 3-15
X-Ref Target - Figure 3-15
M_TXPHDLYRESET
M_TXDLYBYPASS
M_TXPHALIGNEN
M_TXDLYSRESET
M_TXDLYSRESETDONE
M_TXPHINIT
M_TXPHINITDONE
M_TXPHALIGN
M_TXDLYEN
M_TXPHALIGNDONE
S_TXPHDLYRESET
S_TXDLYBYPASS
S_TXPHALIGNEN
S_TXDLYSRESET
S_TXDLYSRESETDONE
S_TXPHINIT
S_TXPHINITDONE
S_TXPHALIGN
S_TXDLYEN
S_TXPHALIGNDONE
Figure 3-15: TX Phase and Delay Alignment, Multi-Lane Mode
Notes relevant to
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Deassert TXPHINIT for the master lane.
11. Assert TXPHALIGN for the master lane. Hold this signal High until the rising edge of
12. Deassert TXPHALIGN for the master lane.
13. Assert TXDLYEN for the master lane. This causes TXPHALIGNDONE to be deasserted.
14. Hold TXDLYEN for the master lane High until the rising edge of TXPHALIGNDONE of the
102
Send Feedback
shows the required steps to perform TX phase and delay alignment.
Figure 3-15:
The sequence of events shown in
M_* denotes ports related to the master lane.
S_* denotes ports related to the slave lane(s).
GTP transceiver: Set the TXSYNC_OVRD attribute to 1'b1.
Set TXPHDLYRESET and TXDLYBYPASS to Low for all lanes.
Set TXPHALIGNEN to High for all lanes.
Assert TXDLYSRESET for all lanes. Hold this signal High until TXDLYSRESETDONE of the
respective lane is asserted.
Deassert TXDLYSRESET for the lane in which the TXDLYSRESETDONE is asserted.
When TXDLYSRESET of all lanes are deasserted, assert TXPHINIT for the master lane. Hold
this signal High until the rising edge of TXPHINITDONE of the master lane is observed.
TXPHALIGNDONE of the master lane is observed.
master lane is observed.
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Figure 3-15 is not drawn to scale.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
UG482_c3_116_020413