Xilinx 7 Series User Manual page 148

Chapter 4: Receiver
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Ports and Attributes
Table 4-17
Table 4-17: RX Fabric Clock Output Control Ports
Port Dir
RXOUTCLKSEL[2:0]
RXRATE[2:0]
RXOUTCLKFABRIC Out
RXOUTCLK Out
RXOUTCLKPCS Out
RXRATEDONE Out
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clock), to clock the downstream fabric logic. It is also used by the RX PCS block. This clock is
interrupted when the PLL or CDR is reset by one of the related reset signals.
RXOUTCLKSEL = 3'b011 or 3'b100: RXPLLREFCLK_DIV1 or
RXPLLREFCLK_DIV2 is the input reference clock to the PLL0 or PLL1 depending on the
RXSYSCLKSEL[1] setting. For usages that do not require outputting a recovered clock to the
fabric, RXPLLREFCLK_DIV1 or RXPLLREFCLK_DIV2 can be used as the system clock.
However, TXOUTCLK is usually used as system clock.
defines the ports required for RX fabric clock output control.
Clock Domain
In Async This port controls the multiplexer select signal in
In RXUSRCLK2 This port dynamically controls the setting for the RX serial clock divider
D (see
(RXRATEMODE
makes this port
asynchronous)
Clock RXOUTCLKFABRIC is a redundant output reserved for testing.
RXOUTCLK with RXOUTCLKSEL = 3'b011 should be used instead.
Clock RXOUTCLK is the recommended clock output to the FPGA logic. The
RXOUTCLKSEL port is the input selector for RXOUTCLK and allows
the PLL input reference clock to the FPGA logic.
Clock RXOUTCLKPCS is a redundant output. RXOUTCLK with
RXOUTCLKSEL = 3'b001 should be used instead.
RXUSRCLK2 The RXRATEDONE port is asserted High for one RXUSRCLK2 cycle in
response to a change on the RXRATE port. The TRANS_TIME_RATE
attribute defines the period of time between a change on the RXRATE
port and the assertion of RXRATEDONE.
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Description
3'b000: Static 1
3'b001: RXOUTCLKPCS path
3'b010: RXOUTCLKPMA path
3'b011: RXPLLREFCLK_DIV1 path
3'b100: RXPLLREFCLK_DIV2 path
Others: Reserved.
Table 4-16
) and it is used with RXOUT_DIV attribute.
3'b000: Use RXOUT_DIV divider value
3'b001: Set D divider to 1
3'b010: Set D divider to 2
3'b011: Set D divider to 4
3'b100: Set D divider to 8
7 Series FPGAs GTP Transceivers User Guide
Figure 4-18 .
UG482 (v1.9) December 19, 2016