Xilinx 7 Series User Manual page 116

Chapter 3: Transmitter
Table 3-28: TX Configurable Driver Ports (Cont'd)
Port
TXMARGIN[2:0]
PMARSVDIN1
PMARSVDIN0
116
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Dir Clock Domain
In Async TX Margin control for PCI Express PIPE 2.0 Interface. These signals are
mapped internally to TXDIFFCTRL/TXBUFDIFFCTRL via attributes.
[2:0]
000
001
010
011
100
101
110
111
In Async Reserved.
In Async Reserved.
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Description
Full Range Half Range
TX_MARGIN_F
800-1200 400-1200
TX_MARGIN_F
800-1200 400-700
TX_MARGIN_F
800-1200 400-700
TX_MARGIN_F
200-400 100-200
TX_MARGIN_F
100-200 100-200
default to "DIRECT" mode
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Full Range Half Range
Attribute Attribute
TX_MARGIN_
ULL_0 LOW_0
TX_MARGIN_
ULL_1 LOW_1
TX_MARGIN_
ULL_2 LOW_2
TX_MARGIN_
ULL_3 LOW_3
TX_MARGIN_
ULL_4 LOW_4