Xilinx 7 Series User Manual page 3

Date Version
10/23/2012 1.3
02/21/2013 1.4
04/15/2013 1.5
08/28/2013 1.6
UG482 (v1.9) December 19, 2016
Added Artix-7 device in Functional Description, page
Model, page 32, and Multiple External Reference Clock Use Model, page
XC7A350T in Figure 3-4 and
XC7A350T devices in Table 5-2
MGTAVCC_G[N} and MGTAVTT_G[N] pins in
Figure A-10, Figure A-11, Figure
Table B-1.
Replaced references to GTX transceiver with references to GTP transceiver throughout
document.
Chapter 2: Updated Figure 2-2,
and Figure 2-17. Updated Table
Reset and Initialization, last paragraph on
Table 2-17, and sections After Power-up and Configuration, page
Source Reset, page 47. Updated
and seventeen. Updated Figure 2-19
and added notes relevant to the figure. Added
including Figure 2-21 and notes relevant to the figure. Revised
Resets, page 56 by adding Table 2-22
through After Comma Realignment, page
page 65. Updated Table 2-28, row two. Updated
rows three and seven. Added
Chapter 3: Revised section TX Buffer Bypass, page 95
Updated Table 3-24, rows three and five, and
Chapter 4: Updated Table 4-3,
row twelve. Added Use Mode, page 132
Modes, page 144 through Table
five. Added section Using RXRATE, page 149
Bypass, page 173 through page
Chapter 5: Updated Table 5-2, rows one and two, and
Appendix A: Updated Figure A-4
Appendix B: Updated Table
Added last two rows in Table
page 25. Changed "DEN" to "DRPEN" in
Figure 2-23 and Figure 2-24. Revised
Table 3-15. Revised TX Buffer Bypass Use Modes, page
Bypass, Single lane Auto mode Port Connection, and replaced
it. Revised Using TX Buffer Bypass in Multi-Lane Mode, page 100
section title and text). Deleted section titled "Using TX Buffer Bypass in Multi Lane Auto Mode."
Added last two rows to Table
Table 4-5. Changed RXCDR_CFG attribute type from 72- to 83-bit hex in
Added devices XC7A35T-CSG325 (Preliminary), XC7A35T-FGG484 (Preliminary),
XC7A50T-CSG325 (Preliminary), XC7A50T-FGG484 (Preliminary), XC7A75T-FGG484, and
XC7A75T-FGG676.
www.xilinx.com
Revision
25,
Figure 3-5 footnotes. Deleted PCIe Protocol in
and Figure 5-3. Added additional ceramic filter capacitor to
Table 5-14. Deleted XC7A350T in
A-12, Figure A-13, and
Figure 2-12, Figure 2-13,
2-6, rows one and two, and
page 40. Updated
Table 2-18, rows two, three, four, seven, twelve, thirteen, fifteen,
and added notes relevant to the figure. Updated
GTP Transceiver RX PMA Reset, page
and sections After Power-up and Configuration, page 47
61. Revised Loopback Functional description on
Table 2-29, rows three and seven and
Digital Monitor, page 70 through
through
Table 3-24, row three.
Table 4-4, Table 4-5, Table
through Figure 4-14, page
4-15. Updated Figure 4-18. Updated
through page
186. Updated Table 4-33
Table
through Figure A-14.
B-1.
2-22. Added three sentences to
Table 2-29 and
TX Buffer Bypass Functional Description, page 93
4-2. Changed "INCP" to "IPCM" in
7 Series FPGAs GTP Transceivers User Guide
Single External Reference Clock Use
33. Deleted
Table 4-3. Deleted
Figure
Figure A-14. Deleted XC7A350T in
Figure 2-14, Figure 2-15, Figure
Table 2-8, rows one and four. Revised
Table 2-14, rows five and six. Added
47, through TX Parallel Clock
Figure 2-20
56,
GTP Transceiver RX Component
Table
page 75.
page 106. Updated Figure
4-6, rows five and six, and Table
138. Added section
Table 4-17, rows three and
150. Revised section RX Buffer
and Table 4-33, rows five and ten.
5-11, rows three and four.
Loopback Functional Description,
Table 2-30. Added a note to
98, deleted Figure 3-12, TX Buffer
Figure 3-12 and notes relevant to
(and removed "Manual" from
Table 4-3, Table 4-4, and
Table 4-12.
A-9,
2-16,
2-30,
3-20.
4-7,
Use
and