Xilinx 7 Series User Manual page 183

X-Ref Target - Figure 4-40
Master
These GTP transceiver settings should be used to bypass the RX buffer:
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With the RX recovered clock selected, RXOUTCLK is to be used as the source of RXUSRCLK.
The user must ensure that RXOUTCLK and the selected RX recovered clock are running and
operating at the desire frequency. When the RX elastic buffer is bypassed, the RX phase alignment
procedure must be performed after these conditions:
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To set up RX buffer bypass in multi-lane auto mode, the following attributes should be set:
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The ports should be set as shown in
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
GTP RX
Lane 3
Slave
RXUSRCLK
RXUSRCLK2
GTP RX
Lane 2
RXUSRCLK
RXUSRCLK2
GTP RX
Lane 1
Slave
RXUSRCLK
RXUSRCLK2
GTP RX
Lane 0
Slave
RXUSRCLK
RXUSRCLK2
Figure 4-40: Example of Buffer Bypass Master versus Slave Lanes
RXBUF_EN = FALSE.
RX_XCLK_SEL = RXUSR.
RXOUTCLKSEL = 010 to select the RX recovered clock as the source of RXOUTCLK.
RXDDIEN = 1.
Resetting or powering up the GTP receiver.
Resetting or powering up the PLL.
Changing the RX recovered clock source or frequency.
Changing the GTP RX line rate.
RXSYNC_MULTILANE = 1
RXSYNC_OVRD = 0
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BUFG
RXOUTCLK
Figure 4-41.
RX Buffer Bypass
BUFG
MMCM/
PLL
UG482_c4_140_020613
183
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