Manual Alignment - Xilinx 7 Series User Manual

Chapter 4: Receiver

Manual Alignment

RXSLIDE can be used to override the automatic comma alignment and to shift the parallel data.
RXSLIDE is driven High for one RXUSRCLK2 cycle to shift the parallel data by one bit. RXSLIDE
must be Low for at least 32 RXUSRCLK2 cycles before it can be used again.
Figure 4-31
PCS, before and after the data shift. When RXSLIDE_MODE = PCS is used, the number of bit shift
positions when consecutive RXSLIDE pulses are issued is also determined by the comma alignment
boundary set by ALIGN_COMMA_WORD and RX_DATA_WIDTH. For example, if the
RX_DATA_WIDTH is 20 bits and ALIGN_COMMA_WORD is 1, after the 9th slide operation, the
slide position returns back to 0. For the same RX_DATA_WIDTH setting, for an
ALIGN_COMMA_WORD setting of 2, the slide position returns to 0 after the 19th slide operation.
X-Ref Target - Figure 4-31
RXUSRCLK2
RXSLIDE
00000000000010011111
RXDATA
TXDATA
Figure 4-31: Manual Data Alignment Using RXSLIDE for RX_DATA_WIDTH = 20 Bits and
Note relevant to
1.
164
Send Feedback
shows the waveforms for manual alignment using RXSLIDE in RXSLIDE_MODE =
A minimum of 32 RXUSRCLK2
cycles are required between two
00000000001001111100
RXSLIDE_MODE = PCS
Figure 4-31:
Latency between the slide and the slide result at RXDATA depends on the number of active RX
PCS blocks in the datapath.
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RXSLIDE pulses
Slide results on RXDATA
after several cycles of latency
through the PCS path
00000000000100111110
7 Series FPGAs GTP Transceivers User Guide
00000000001001111100
UG482_c4_20_111011
UG482 (v1.9) December 19, 2016