Xilinx 7 Series User Manual page 24

Chapter 2: Shared Features
Ports and Attributes
Table 2-1
Table 2-1: Reference Clock Input Ports (IBUFDS_GTE2)
I
IB
CEB
O
ODIV2
Notes:
1. The O and ODIV2 outputs are not phase matched to each other.
Table 2-2
reference clock input.
Table 2-2: Reference Clock Input Attributes (IBUFDS_GTE2)
CLK_RCV_TRST
CLKCM_CFG
CLKSWING_CFG
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defines the reference clock input ports in the IBUFDS_GTE2 software primitive.
Port Dir Clock Domain
In (pad)
In
Out
(1)
Out
defines the attributes in the IBUFDS_GTE2 software primitive that configure the
Attribute Type
Boolean
Boolean
2-bit Binary
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N/A These are the reference clock input ports that get
mapped to GTREFCLK0P/GTREFCLK0N and
GTREFCLK1P/GTREFCLK1N.
N/A This is the active-Low asynchronous clock
enable signal for the clock buffer. Setting this
signal High powers down the clock buffer.
N/A This output drives the GTREFCLK[0/1] signals
in the GTPE2_COMMON software primitives.
Refer to Reference Clock Selection and
Distribution, page 25
This output can also drive the BUFG or BUFH
software primitives via Hrow routing. Only one
of the IBUFDS_GTE2's O or ODIV2 outputs can
be routed to the FPGA logic. The selection is
controlled automatically by the software
depending on whether port O or ODIV2 is
connected. Refer to UG472, 7 Series FPGAs
Clocking Resources User Guide for more details.
N/A This output is a divide-by-2 version of the O
signal, which can drive the BUFG or BUFH
software primitives via Hrow routing. The
selection is controlled automatically by the
software depending on whether port O or ODIV2
is connected. Refer to UG472, 7 Series FPGAs
Clocking Resources User Guide for more details.
Description
Reserved. This attribute switches the 50Ω termination
resistors into the signal path. This attribute must always
be set to TRUE.
Reserved. This attribute switches in the termination
voltage for the 50Ω termination. This attribute must
always be set to TRUE.
Reserved. This attribute controls the internal swing of the
clock. This attribute must always be set to 2'b11.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Description
for more details.