Xilinx 7 Series User Manual page 138

Chapter 4: Receiver
X-Ref Target - Figure 4-13
X-Ref Target - Figure 4-14
138
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PCIe Gen2 Exit
Is RXELECIDLE
Deasserted?
Yes
Valid EIOS?
Yes
RX is Out of Electrical Idle
Figure 4-13: Flowchart for Exit from RX Electrical Idle for PCIe Gen2
SATA 3G or 6G
Is RXELECIDLE
Asserted?
Yes
Is Incoming Data
Valid?
No
RX is in Electrical Idle
Figure 4-14: Flowchart for SATA 3G or SATA 6G
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No
No
UG482_c4_113_020413
No
Yes
RX is Not in Electrical Idle
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
UG482_c4_114_020413