Xilinx 7 Series User Manual page 35

X-Ref Target - Figure 2-9
The PLL input clock selection is described in
The PLL outputs feed the TX and RX clock divider blocks, which control the generation of serial
and parallel clocks used by the PMA and PCS blocks.
Figure 2-10
a factor of M before feeding into the phase frequency detector. The feedback dividers N1 and N2
determine the VCO multiplication ratio and the PLL output frequency. A lock indicator block
compares the frequencies of the reference clock and the VCO feedback clock to determine if a
frequency lock has been achieved.
X-Ref Target - Figure 2-10
The PLL has a nominal operating range between 1.6 GHz to 3.3 GHz. The 7 Series FPGAs
Transceivers Wizard chooses the appropriate PLL settings based on application requirements.
Equation 2-1
Equation 2-2
clock divider block in the channel.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
GTPE2_COMMON
REFCLK
Distribution
Figure 2-9: Internal Clocking Architecture
illustrates a conceptual view of the PLL architecture. The input clock can be divided by
PLL
CLKIN
Phase
/ M
Frequency
Detector
Figure 2-10: PLL Block Diagram
shows how to determine the PLL output frequency (GHz).
f
PLLClkout
shows how to determine the line rate (Gb/s). D represents the value of the TX or RX
f
LineRate
www.xilinx.com
GTPE2_CHANNEL
PLL0
PLL1
Reference Clock Selection and Distribution, page
Lock
Indicator
Charge
Loop
Pump
Filter
/ N1
/ N2
×
N1 N2
×
= f -------------------- -
PLLClkin
M
×
f 2
PLLClkout
= ---------------------------------- -
D
PLL
TX TX PMA
Clock
TX PCS
Dividers
RX RX PMA
Clock
RX PCS
Dividers
UG482_c2_09_110811
25.
PLL
LOCKED
PLL
CLKOUT
VCO
UG482_c2_10_011612
Equation 2-1
Equation 2-2
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