Tx Fabric Clock Output Control - Xilinx 7 Series User Manual

Ports and Attributes
Table 3-22
Table 3-22: TX Polarity Control Ports
TXPOLARITY
Using TX Polarity Control
TXPOLARITY can be tied High if the polarity of TXP and TXN needs to be reversed.

TX Fabric Clock Output Control

Functional Description
The TX Clock Divider Control block has two main components: serial clock divider control and
parallel clock divider and selector control. The clock divider and selector details are illustrated in
Figure
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
defines the ports required for TX polarity control.
Port Dir Clock Domain
In TXUSRCLK2
3-20.
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TX Fabric Clock Output Control
Description
The TXPOLARITY port is used to invert the polarity
of outgoing data.
0: Not inverted. TXP is positive, and TXN is
negative.
1: Inverted. TXP is negative, and TXN is positive.
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