Rx Overview - Xilinx 7 Series User Manual

Receiver

RX Overview

Functional Description
This section shows how to configure and use each of the functional blocks inside the receiver (RX).
Each GTP transceiver includes an independent receiver, made up of a PCS and a PMA.
shows the blocks of the GTP transceiver RX. High-speed serial data flows from traces on the board
into the PMA of the GTP transceiver RX, into the PCS, and finally into the FPGA logic. Refer to
Figure 2-9, page 35
to the RX and TX clock dividers.
X-Ref Target - Figure 4-1
From TX Parallel
Clock from Data (Near-End
PLL0 or PLL1 PCS Loopback)
RX
Clock
Dividers
RX EQ
SIPO
RX OOB
The key elements within the GTP transceiver RX are:
1.
2.
3.
4.
5.
6.
7.
8.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
for the description of the channel clocking architecture, which provides clocks
To TX Parallel
Data (Far-End
PMA Loopback)
Comma
Detect
Polarity
and
Align
PRBS
Checker
Figure 4-1: GTP Transceiver RX Block Diagram
RX Analog Front End, page 126
RX Out-of-Band Signaling, page 131
RX Equalizer, page 139
RX CDR, page 141
RX Fabric Clock Output Control, page 147
RX Margin Analysis, page 151
RX Polarity Control, page 158
RX Pattern Checker, page 159
www.xilinx.com
Data (Far-End PCS
RX PIPE
Control
RX Status
Control
8B/10B
Decoder
RX
Elastic
Buffer
Chapter 4
Figure 4-1
To TX Parallel
Loopback)
FPGA RX
Interface
RX
Gearbox
UG482_c4_01_110911
125
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