Xilinx 7 Series User Manual page 90

Chapter 3: Transmitter
Due to the nature of the 64B/66B and 64B/67B encoding schemes, user data is held (paused) during
various sequence counter values. Data is paused for two TXUSRCLK2 cycles in 2-byte mode and
for one TXUSRCLK2 cycle in 4-byte mode. Valid data transfer is resumed on the next
TXUSRCLK2 cycle. The data pause only applies to TXDATA and not to TXHEADER. The
TXSEQUENCE pause locations for various modes are described in
Table 3-10: 64B/66B Encoding Frequency of TXSEQUENCE and Pause Locations
Table 3-11: 64B/67B Encoding Frequency of TXSEQUENCE and Pause Locations
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TX_DATA_WIDTH
32
(4-byte)
16
(2-byte)
TX_DATA_WIDTH
32
(4-byte)
16
(2-byte)
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Table 3-10
Frequency of
TXSEQUENCE
1 X
TXUSRCLK2
2 X
TXUSRCLK2
Frequency of
TXSEQUENCE
1 X
TXUSRCLK2
2 X
TXUSRCLK2
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
and Table 3-11.
TXSEQUENCE PAUSE
31
31
TXSEQUENCE PAUSE
21, 44, 65
21, 44, 65