Xilinx 7 Series User Manual page 208

Chapter 4: Receiver
X-Ref Target - Figure 4-53
Figure 4-54
64B/66B encoding when using a 2-byte logic interface (RX_DATA_WIDTH = 16 (2-byte)).
208
Send Feedback
Design in FPGA Logic
Figure 4-53: Gearbox in Either Internal or External Sequence Mode
shows an example of five cycles of data entering and exiting the RX gearbox for
www.xilinx.com
RXDATA[15:0] or RXDATA[31:0]
RXHEADER[2:0]
RXDATAVALID[1:0]
RXHEADERVALID
RXSTARTOFSEQ
RXGEARBOXSLIP
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
RX Gearbox
(in 7 Series FPGAs
GTP Transceiver)
UG482_c4_35_111011