Xilinx 7 Series User Manual page 232

Chapter 5: Board Design Guidelines
Another choice is to mount an 0201 capacitor next to the BGA via pads. Doing this eliminates the
need to use filled via in pad. An example of this placement is shown in
X-Ref Target - Figure 5-12
View From Bottom of PCB
Figure 5-12: Placement of 0.1 µF 0201 Capacitor on Bottom of PCB Under FPGA
The Artix-7 FPGA and Zynq-7000 AP SoC packages with GTP transceivers have analog power
supply pins and adjacent ground pins.
ground pin pairs for mounting the 0.1 µF capacitors. Following the guidance in these tables and
using the previously discussed layout and placement guidance provides effective power supply
decoupling by maintaining a minimum amount of inductance in the path between the on-die
circuitry and the capacitor on the printed circuit board.
Table 5-8: CLG485 Package – 0.1 µF Capacitor Placement
Table 5-9: CPG236 Package – 0.1 µF Capacitor Placement
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0201 Capacitor
Capacitor
MGTAVCC
Cap1
Cap2
Cap3 U8
Cap4 W5
Capacitor
MGTAVCC
Cap1
Cap2
Cap3 H9
Cap4 C1
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1 mm.
BGA Pin Field Vias
1 mm.
Cover Via With
Solder Mask
UG482_c5_12_072412
Table 5-8 through Table 5-13
Package Pins
MGTAVTT
Y7
AA4
Package Pins
MGTAVTT
G7
B1
7 Series FPGAs GTP Transceivers User Guide
Figure 5-12.
show suggested power and
Value
GND
W7
AB4
0.1 µF
V8
Y5
Value
GND
G8
0.1 µF
A1
H8
0.1 µF
C2
UG482 (v1.9) December 19, 2016