Xilinx 7 Series User Manual page 134

Chapter 4: Receiver
Figure 4-8
dividers such as divide-by-4 and divide-by-8.
X-Ref Target - Figure 4-8
Use Modes
For OOB operating at a line rate of 1.5 Gb/s or below, see the flowchart in
the frequency f of the OOB clock.
X-Ref Target - Figure 4-9
The requirement in
OOB operating at line rates > 1.5 Gb/s is an advanced feature. Operation for certain protocols at
higher line rates such as PCIe (Gen1 and Gen2) and SATA are addressed in
134
Send Feedback
shows how cascading several divide-by-two circuits produces higher order clock
Clk div2
Figure 4-8: Clock Dividers
For Linerate ≤ 1.5 Gb/s
f ≤ Linerate / (3 x Runlength)
Is RXELECIDLE
Asserted?
Yes
RX is in Electrical Idle
Figure 4-9: Flowchart for Protocols with Line Rates < 1.5G
Equation 4-1 must be satisfied for the OOB to work correctly.
≤ ⁄
f linerate
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Clk/2
div2 div2
Clk/4
No
RX is Not in Electrical Idle
( × )
3 runlength
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Clk/8
UG482_c4_108_020413
Figure 4-9 to determine
UG482_c4_109_0020413
Equation 4-1
Table 4-8.