Xilinx 7 Series User Manual page 21
Fpgas gtp transceivers
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X-Ref Target - Figure 1-5
Serial Transceiver Channels by Device/Package
See UG475, 7 Series FPGAs Packaging and Pinout Specification.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
GTPE2_COMMON
IBUFDS_GTE2
GTREFCLK0
Figure 1-5: Four Channel Configuration
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GTPE2_CHANNEL
PLL0
PLL1
GTPE2_CHANNEL
GTPE2_CHANNEL
GTPE2_CHANNEL
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Implementation
TX
RX
TX
RX
TX
RX
TX
RX
UG482_c1_05_110811
21
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- Dynamic Reconfiguration Port
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