Xilinx 7 Series User Manual page 267

Table D-2
Note:
automatically by the 7 Series FPGAs Transceivers Wizard. These attributes must be left at their
defaults, except for use cases that explicitly request different values.
Table D-2: DRP Map of GTPE2_CHANNEL Primitive
DRP
DRP Bits
Address
15
0000
14
0000
13
0000
1
0000
15:11
000C
14:10
000D
9:5
000D
4:0
000D
11:7
000E
6:0
000E
11:7
000F
15
0010
14
0010
13
0010
12
0010
11
0010
10
0010
9:5
0010
4:0
0010
14
0011
13:11
0011
10:6
0011
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
lists the DRP map of the GTPE2_CHANNEL primitive sorted by address.
The reserved bits should NOT be modified. Attributes that are not described explicitly are set
R/W Attribute Name
R/W ACJTAG_RESET
R/W ACJTAG_DEBUG_MODE
R/W ACJTAG_MODE
R/W UCODEER_CLR
R/W RXBUFRESET_TIME
R/W RXCDRPHRESET_TIME
R/W RXCDRFREQRESET_TIME
R/W RXPMARESET_TIME
R/W RXPCSRESET_TIME
R/W RXLPMRESET_TIME
R/W RXISCANRESET_TIME
R/W RXSYNC_OVRD
R/W TXSYNC_OVRD
R/W RXSYNC_SKIP_DA
R/W TXSYNC_SKIP_DA
R/W TXSYNC_MULTILANE
R/W RXSYNC_MULTILANE
R/W TXPCSRESET_TIME
R/W TXPMARESET_TIME
R/W RX_XCLK_SEL
R/W RX_DATA_WIDTH
R/W RX_CLK25_DIV
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Attribute Attribute
Bits Encoding
0 0-1
0 0-1
0 0-1
0 0-1
4:0 0-31
4:0 0-31
4:0 0-31
4:0 0-31
4:0 0-31
6:0 0-127
4:0 0-31
0 0-1
0 0-1
0 0-1
0 0-1
0 0-1
0 0-1
4:0 0-31
4:0 0-31
RXREC
0
RXUSR
16
20
2:0
32
40
1
2
4:0
3
4
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DRP
Encoding
0-1
0-1
0-1
0-1
0-31
0-31
0-31
0-31
0-31
0-127
0-31
0-1
0-1
0-1
0-1
0-1
0-1
0-31
0-31
0
1
2
3
4
5
0
1
2
3
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