Xilinx 7 Series User Manual page 175

Table 4-29: RX Buffer Bypass Ports (Cont'd)
RXPHDLYPD
RXPHOVRDEN
RXDLYSRESET
RXDLYBYPASS
RXDLYEN
RXDLYOVRDEN
RXDDIEN
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Port Dir
In
In
In
In
In
In
In
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Clock Domain
Async RX phase and delay alignment circuit
power down. Tied High when a) RX
buffer bypass is not in use;
b) RXPD is asserted or
c) RXOUTCLKSEL is set to 3'b010
but the recovered clock is not available.
Tied Low during RX buffer bypass mode
normal operation.
0: Power-up the RX phase and delay
alignment circuit.
1: Power-down the RX phase and
delay alignment circuit.
Async RX phase alignment counter override
enable. Tied Low when not in use.
0: Normal operation.
1: Enables the RX phase alignment
counter override with the
RXPH_CFG[10:6] value.
Async RX delay alignment soft reset to
gradually shift RXUSRCLK to the center
of the delay alignment tap. The delay
alignment tap has a full range of ±4 ns
and a half range of ±2 ns. This soft reset
can be used to initiate the GTP
transceiver to perform the RX phase and
delay alignment automatically when all
other RX bypass buffer input ports are
Low.
Async RX delay alignment bypass.
0: Uses the RX delay alignment
circuit.
1: Bypasses the RX delay alignment
circuit.
Async RX delay alignment enable. Tied Low
when not in use.
Async RX delay alignment counter override
enable. Tied Low when not in use.
0: Normal operation.
1: Enables the RX delay alignment
counter override with the
RXDLY_CFG[14:6] value.
Async RX data delay insertion enable in the
deserializer. Set High in RX buffer
bypass mode.
RX Buffer Bypass
Description
175
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