Xilinx 7 Series User Manual page 62

Chapter 2: Shared Features
Table 2-23: Power-Down Ports (Cont'd)
TXPD[1:0]
TXPDELECIDLEMODE
TXPHDLYPD
RXPHDLYPD
Table 2-24
Table 2-24: Power-Down Attributes
PD_TRANS_TIME_FROM_P2
PD_TRANS_TIME_NONE_P2
62
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Port Dir
In
(TXPDELECIDLEMODE
In
In
In
defines the power-down attributes.
Attribute
12-bit Hex
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Clock Domain
TXUSRCLK2 Powers down the TX lane
according to the PCI Express
makes this port PIPE protocol encoding.
asynchronous)
Attributes can control the
transition times between these
power-down states.
Async Determines if TXELECIDLE and
TXPD should be treated as
synchronous or asynchronous
signals.
Async TX phase and delay alignment
circuit power down. It is set to
1'b0 in TX buffer bypass mode.
Async RX phase and delay alignment
circuit power down. It is set to
1'b0 in RX buffer bypass mode.
Type
Counter settings for programmable
transition time from P2 state for PCIe. The
recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
8-bit Hex Counter settings for programmable
transition time to/from all states except P2
for PCIe. The recommended value from the
7 Series FPGAs Transceivers Wizard
should be used.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Description
00: P0 (normal operation)
01: P0s (low recovery time
power down)
10: P1 (longer recovery time;
Receiver Detection still on)
11: P2 (lowest power state)
0: Power up the TX phase and
delay alignment circuit.
1: Power down the TX phase
and delay alignment circuit.
0: Power up the RX phase and
delay alignment circuit.
1: Power down the RX phase
and delay alignment circuit.
Description