Xilinx 7 Series User Manual page 151

Eye Scan Theory
RXDATA is recovered from the equalized differential waveform by sampling after the RX
equalizer. The horizontal sampling position is determined by the CDR function and the vertical
position is differential zero. This is indicated as data sample in
To enable eye scan functionality, an additional sampler is provided with programmable (horizontal
and vertical) offsets from the data sample point. This is indicated as offset sample in
A single eye scan measurement consists of accumulating the number of data samples (sample count)
and the number of times that the offset sample disagreed with the data sample (error count). The bit
error ratio (BER) at the programmed vertical and horizontal offset is the ratio of the error count to
the sample count. The sample count can range from tens of thousands to greater than 10
Repeating such BER measurements for the full array of horizontal and vertical offsets (or a
subsampled set of offsets) produces a BER map as shown in
a statistical eye, where the color map represents log
smaller than a traditional oscilloscope view (as in
low probability jitter and noise that does not show up in the much lower number of samples of an
oscilloscope.
Because this functionality puts no restrictions on the data patterns being received nor requires any
changes in the RX settings, it can be performed while application data is being received without
error. Furthermore, no FPGA logic is required—only the ability to read and write attributes.
Eye Scan Architecture
The blocks with shaded gray in
supports eye scan. The horizontal offset (HORZ_OFFSET) advances or delays the sampling time of
the offset samples relative to the data samples. The vertical offset (VERT_OFFSET) raises or lowers
the differential voltage threshold to which the equalized waveform is compared. The data samples
are deserialized into the Rdata bus, and the offset samples are deserialized into the Sdata bus.
X-Ref Target - Figure 4-21
RX Input
Equalization
VERT_OFFSET
DAC
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 4-21
Capture FF
+
Rec Clock
Figure 4-21: PMA Architecture to Support Eye Scan
www.xilinx.com
Figure
Figure
(BER). In this view, the eye is apparently
10
Figure 4-20) because it has been closed by very
describe the portion of the PMA architecture that
Error-detection,
Screening
De-serialization
Capture FF
PI PI
HORZ_OFFSET
RX Margin Analysis
4-20.
Figure 4-20.
14
.
4-20, commonly referred to as
Rdata
PCS
Interface
Sdata
UG482_c4_10_112811
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