Xilinx 7 Series User Manual page 296

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
15
004B
9:0
004B
15:12
004C
9:0
004C
15:14
004D
9:0
004D
15
004E
9:0
004E
9:0
004F
15:12
0050
11
0050
9:0
0050
15:12
0051
11
0051
9:0
0051
15:12
0052
11
0052
9:0
0052
15:12
0053
296
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R/W Attribute Name
R/W RXGEARBOX_EN
R/W CLK_COR_SEQ_2_4
R/W CHAN_BOND_SEQ_1_ENABLE
R/W CHAN_BOND_SEQ_1_1
R/W CHAN_BOND_SEQ_LEN
R/W CHAN_BOND_SEQ_1_2
R/W CHAN_BOND_KEEP_ALIGN
R/W CHAN_BOND_SEQ_1_3
R/W CHAN_BOND_SEQ_1_4
R/W CHAN_BOND_SEQ_2_ENABLE
R/W CHAN_BOND_SEQ_2_USE
R/W CHAN_BOND_SEQ_2_1
R/W FTS_LANE_DESKEW_CFG
R/W FTS_LANE_DESKEW_EN
R/W CHAN_BOND_SEQ_2_2
R/W FTS_DESKEW_SEQ_ENABLE
R/W CBCC_DATA_SOURCE_SEL
R/W CHAN_BOND_SEQ_2_3
R/W CHAN_BOND_MAX_SKEW
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Attribute Attribute
Bits Encoding
FALSE
0
TRUE
9:0 0-1023
3:0 0-15
9:0 0-1023
1
2
1:0
3
4
9:0 0-1023
FALSE
0
TRUE
9:0 0-1023
9:0 0-1023
3:0 0-15
FALSE
0
TRUE
9:0 0-1023
3:0 0-15
FALSE
0
TRUE
9:0 0-1023
3:0 0-15
ENCODED
0
DECODED
9:0 0-1023
1
2
3
3:0
4
5
6
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0
1
0-1023
0-15
0-1023
0
1
2
3
0-1023
0
1
0-1023
0-1023
0-15
0
1
0-1023
0-15
0
1
0-1023
0-15
0
0
0-1023
1
2
3
4
5
6