Reset And Initialization - Xilinx 7 Series User Manual

Chapter 2: Shared Features
Table 2-9: PLL Attributes (Cont'd)
PLL0_INIT_CFG
PLL1_INIT_CFG
PLL0_DMON_CFG
PLL1_DMON_CFG

Reset and Initialization

The GTP transceiver must be initialized after FPGA device power-up and configuration before it
can be used. The GTP transceiver's transmitter (TX) and receiver (RX) can be initialized
independently and in parallel as shown in
initialization comprises two steps:
1.
2.
The GTP transceiver's TX and RX can receive a clock from either PLL0 or PLL1. The associated
PLL (PLL0 /PLL1) used by the TX and RX must be initialized first before TX and RX initialization.
Any PLL used by the TX and RX is reset individually and its reset operation is completely
independent from all TX and RX resets. The TX and RX datapaths must be initialized only after the
associated PLL is locked.
X-Ref Target - Figure 2-11
38
Send Feedback
Attribute
24-bit Hex
1-bit Binary
Initializing the associated PLL driving TX/RX
Initializing the TX and RX datapaths (PMA + PCS)
Initialize PLL
(PLL0/PLL1)
used by TX
TX Initialization By
GTTXRESET
TXRESETDONE
Figure 2-11: GTP Transceiver Initialization Overview
www.xilinx.com
Type
Reserved. The recommended value from the 7 Series
FPGAs Transceivers Wizard should be used.
Reserved. The recommended value from the 7 Series
FPGAs Transceivers Wizard should be used.
Figure 2-11. The GTP transceiver's TX and RX
After FPGA
Configuration
Initialize PLL
(PLL0/PLL1)
used by RX
RX Initialization By
GTRXRESET
RXRESETDONE
7 Series FPGAs GTP Transceivers User Guide
Description
UG482_c2_15_040412
UG482 (v1.9) December 19, 2016