Xilinx 7 Series User Manual page 279

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0015
12:6
(Cont'd)
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W SAS_MAX_COM
www.xilinx.com
Attribute Attribute
Bits Encoding
67
68
69
70
71
71
73
74
75
76
77
78
79
80
81
82
6:0
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Send Feedback
DRP
Encoding
67
68
69
70
71
71
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
279