Tx Buffer Bypass - Xilinx 7 Series User Manual

Table 3-14: TX Buffer Attributes (Cont'd)
TX_XCLK_SEL
TXBUF_RESET_ON_RATE_CHANGE
Using the TX Buffer
The TX buffer should be reset whenever TXBUFSTATUS indicates an overflow or underflow
condition. The TX buffer can be reset by using GTTXRESET, TXPCSRESET, or the GTP
transceiver internally generated TX buffer reset on rate change when
TXBUF_RESET_ON_RATE_CHANGE = TRUE. Assertion of GTTXRESET triggers a sequence
that resets the entire transmitter of the GTP transceiver. These settings are use to enable the TX
buffer to resolve phase differences between the XCLK and TXUSRCLK domains:
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TX Buffer Bypass

Functional Description
Bypassing the TX buffer is an advanced feature of the 7 series GTP transceiver. The TX
phase-alignment circuit is used to adjust the phase difference between the PISO parallel clock
domain and the TX XCLK domain to transfer data from the PCS into the PISO. It also performs the
TX delay alignment by continuously adjusting the TXUSRCLK to compensate for temperature and
voltage variations. The combined TX phase and delay alignments must be manually controlled by
the user.
describes the trade-offs between buffering and phase alignment.
Ports and Attributes
Table 3-15
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Attribute
TXBUF_EN = TRUE
TX_XCLK_SEL = TXOUT
Figure 3-11, page 93 shows the XCLK and TXUSRCLK domains.
defines the TX buffer bypass ports.
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Type Description
String Selects the clock source used to drive
the PMA parallel clock domain
(XCLK).
TXOUT: Selects TXOUTCLK as
source of XCLK. Use when using
the TX buffer.
TXUSR: Selects TXUSRCLK as
source of XCLK. Used when
bypassing the TX buffer.
String GTP transceiver internally generated
TX buffer reset on rate change.
TRUE: Enables auto TX buffer reset
on rate change.
FALSE: Disables auto TX buffer
reset on rate change.
Table 3-12, page 94
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TX Buffer Bypass
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