Xilinx 7 Series User Manual page 92

Chapter 3: Transmitter
9.
10. On count 65, stop data pipeline.
11. On count 66, drive data on TXDATA.
The sequence of transmitting 64/66 data for the external sequence counter mode is as follows:
1.
2.
3.
4.
5.
6.
7.
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Send Feedback
On count 45, drive data on TXDATA.
Apply GTTXRESET and wait until the reset cycle is completed.
During reset, apply 6'h00 to TXSEQUENCE, the appropriate header data to TXHEADER,
and initial data to TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, apply data to TXDATA and header information to TXHEADER. For a 2-byte
interface (TX_DATA_WIDTH = 16), drive the second 2 bytes to TXDATA while still on count
0.
The sequence counter increments to 1 while data is driven on TXDATA.
After applying 4 bytes of data, the counter increments to 2. Drive data on TXDATA and header
information on TXHEADER.
On count 31, stop data pipeline.
On count 32, drive data on TXDATA.
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UG482 (v1.9) December 19, 2016