Xilinx 7 Series User Manual page 79

TXOUTCLK Driving GTP Transceiver TX in 2-Byte Mode
In
(TX_DATA_WIDTH = 16 or 20) in a single-lane configuration. The frequency of TXUSRCLK2 is
equal to TXUSRCLK.
X-Ref Target - Figure 3-2
Notes relevant to
1.
2.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 3-2, TXOUTCLK is used to drive TXUSRCLK and TXUSRCLK2 for 2-byte mode
TXOUTCLK
TXUSRCLK2
7 Series FPGAs
GTP Transceiver
TXUSRCLK
TXDATA (TX_DATA_WIDTH = 16 / 20 bits)
Figure 3-2: Single Lane—TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode)
Figure 3-2:
BUFH can be used with certain limitations. For details about placement constraints and
restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472, 7 Series
FPGAs Clocking Resources User Guide.
F = F
TXUSRCLK2 TXUSRCLK
www.xilinx.com
1
BUFG
2
2
.
FPGA TX Interface
Design in
FPGA
UG482_c3_02_110911
79
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