Xilinx Virtex UltraScale+ FPGAs User Manual
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Xilinx Virtex UltraScale+ FPGAs User Manual

Xilinx Virtex UltraScale+ FPGAs User Manual

Gtm transceivers
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Virtex UltraScale+ FPGAs
GTM Transceivers
User Guide
UG581 (v1.0) January 4, 2019

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Summary of Contents for Xilinx Virtex UltraScale+ FPGAs

  • Page 1 Virtex UltraScale+ FPGAs GTM Transceivers User Guide UG581 (v1.0) January 4, 2019...

  • Page 2: Revision History

    Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 01/04/2019 Version 1.0 Initial Xilinx release. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 3: Table Of Contents

    TX Gray Encoder........................71 TX Pre-Coder..........................72 TX Fabric Clock Output Control....................73 TX Configurable Driver......................77 Chapter 4: Receiver ......................84 RX Analog Front End......................... 85 RX Equalizer..........................87 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 4 UltraScale+ FGPAs ....................133 GTM_DUAL Primitive DRP Address Map................133 Appendix B: Additional Resources and Legal Notices ......143 Xilinx Resources........................143 Documentation Navigator and Design Hubs..............143 Please Read: Important Legal Notices................. 144 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback...

  • Page 5: Chapter 1: Transceiver And Tool Overview

    Chapter 1 Transceiver and Tool Overview Introduction to the UltraScale Architecture The Xilinx ® UltraScale™ architecture is the first ASIC-class architecture to enable multi-hundred gigabit-per-second levels of system performance with smart processing, while efficiently routing and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of...

  • Page 6: Features

    14.5 Gb/s – 9.8 Gb/s ○ The GTM transceiver is Xilinx’s first PAM4 enabled transceiver that is highly configurable and tightly integrated with the programmable logic resources of the FPGA. The table below summarizes the features by functional group that support a wide variety of applications.
  • Page 7 • CPRI at 48 Gb/s, 24 Gb/s, 12 Gb/s, and 10.1 Gb/s The first-time user is recommended to read High-Speed Serial I/O Made Simple, which discusses high-speed serial transceiver technology and its applications. The Xilinx Vivado ® IP catalog includes an UltraScale+ FPGAs GTM Transceivers Wizard to automatically configure GTM transceivers to support configurations for different protocols and perform custom configurations.
  • Page 8 UltraScale+ device transceivers such as the GTH and GTY transceivers, the GTM transceiver does not contain channel/common primitives. All channel ports and attributes are within the GTM_DUAL primitive. The following figure illustrates the topology of a GTM channel. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 9: Ultrascale+ Fpgas Gtm Transceivers Wizard

    RECOMMENDED: Download the most recent IP update before using the Wizard. Details on how to use this Wizard can be found in the UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315). UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 10: Simulation

    SIM_DEVICE String This attribute selects the simulation version to match different versions of silicon. The default for this attribute is ULTRASCALE_PLUS. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 11: Implementation

    GTM Channel 0 (CH0) IBUFDS_GTM LCPLL GTM Channel 1 (CH1) X20212-061418 Each dual contains an LCPLL. Therefore, a reference clock can be connected directly to a GTM_DUAL primitive. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 12: Chapter 2: Shared Features

    Reference Clock Input Structure Figure 4: IBUFDS_GTM MGTAVCC Nominal To GTREFCLK or GTREFCLKP 50Ω GTM_DUAL - MGTAVCC Nominal GTREFCLKN 50Ω 2'b00 2'b01 HROW ODIV2 1'b0 2'b10 Reserved 2'b11 REFCLK_HROW_CK_SEL X20917-061418 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 13 OBUFDS_GTM primitive is shown in the following figure. The ports and attributes controlling the reference clock output are tied to the OBUFDS_GTM software primitive. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 14: Reference Clock Selection And Distribution

    Reserved. Use the recommended value from the Wizard. Reference Clock Selection and Distribution The GTM transceivers in Virtex UltraScale+ FPGAs provide different reference clock input options. Clock selection and availability is similar to the GTY transceivers in UltraScale+ devices, but the reference clock selection architecture supports only one LCPLL shared per Dual (two GTM transceiver channels).
  • Page 15 A single reference clock is most commonly used. In the case of a single reference clock, connect the reference clock to the GTREFCLK ports and tie the PLLREFCLKSEL ports to 3’b001. The Xilinx software tools handle the complexity of the multiplexers and associated routing.
  • Page 16 IBUFDS_GTM output (O) to the GTREFCLK ports of the GTM_DUAL primitives. In this case, the Xilinx implementation tools make the necessary adjustments to the north/south routing as well as the pin swapping necessary to route the reference clock from one Dual to another when required.
  • Page 17 MGTREFCLKP and MGTREFCLKN can only be used as long as the GTPOWERGOOD signal has already asserted High. Ports and Attributes The following table defines the clocking ports and attributes for the GTM_DUAL primitive. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 18: Lcpll

    Each Dual contains one LC-based PLL, referred to as LCPLL, and cannot be shared with neighboring Duals. The internal clocking architecture of the GTM Dual is shown in the following figure. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 19 VCO frequency. A lock indicator block compares the frequencies of the reference clock and VCO feedback clock to determine if a frequency lock has been achieved. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 20 Filter Detector /N-Fractional LCPLLCLKOUT_RATE X20901-052418 The LCPLL VCO operates within 9.8 GHz—14.5 GHz. The Xilinx software tool chooses the appropriate LCPLL setting based on application requirements. Equation 2-1 shows how to determine the PLL output frequency (GHz). N + FractionalDivider...
  • Page 21 Reserved. This port must be set to 5’b11111. Do not modify this value. BGRCALOVRDENB Async Reserved. This port must be set to 1’b1. Do not modify this value. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 22 Reserved. Use the recommended value from the Wizard. PLL_CFG5 16-bit Reserved. Use the recommended value from the Wizard. PLL_CFG6 16-bit Reserved. Use the recommended value from the Wizard. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 23: Reset And Initialization

    The LCPLL used by the TX and RX is reset individually and its reset operation independent from TX and RX resets. The TX and RX datapaths must be initialized only after the associated LCPLL is locked. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 24 GTRXRESET port. Separate component reset ports are available. For the TX, these are TXCKALRESET, TXFECRESET, TXPCSRESET, and TXPMARESET. For the RX, these are RXADAPTRESET, RXADCCLKGENRESET, RXBUFRESET, RXCDRFRRESET, RXCDRPHRESET, RXDFERESET, RXDSPRESET, RXEYESCANRESET, RXFECRESET, RXPCSRESET, RXPMARESET, and RXPRBSCSCNTRST. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 25 50 ns before the assertions of any reset. Table 11: GTM Transceiver Reset Modes Operation Operation Mode (TX/RX)RESETMODE Sequential Mode 2'b00 Single Mode 2'b11 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 26 Active-High LCPLL frequency lock signal indicates that the LCPLL frequency is within a predetermined tolerance. The GTM transceiver and its clock outputs are not reliable until this condition is met. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 27 TX FEC Reset TXPCSRESETMASK[0] = 1? = 1? TXPMARESETMASK[1] TX PMA Top Reset TXPCSRESETMASK[1] TX PCS Top Reset = 1? = 1? TXRESETDONE High Wait for TXUSERRDY X20905-060518 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 28 Async This port is driven High and then deasserted to start a single mode reset on TX PCS. The reset is not dependent on TXRESETMODE or TXPCSRESETMASK setting. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 29 Reserved. Use the recommended value from the Wizard. CH[0/1]_RST_LP_CFG4 1-bit Reserved. Bit Name Address Description BYP_HDSHK_TX_PCS_RESET_LOOP Reserved. Use the recommended value from the Wizard. BYP_HDSHK_TX_CKCAL_RESET_LOOP Reserved. Use the recommended value from the Wizard. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 30 GTTXRESET an active-High pulse. These conditions must be met when using GTTXRESET: 1. TXRESETMODE must be set to sequential mode. 2. All TXPMARESETMASK and TXPCSRESETMASK bits should be held High during the reset sequence before TXRESETDONE is detected High. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 31 TXPMARESETMASK, TXPCSRESETMASK, and TXRESETMODE selection. These ports must be held Low during any sequential or single resets driven by GTTXRESET. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 32 PLL, Entire TX 2'b00 2’b11 2’b11 reference clock to the PLL being used After assertion/ PLL, Entire TX 2'b00 2’b11 2’b11 deassertion of PLLPD for the PLL being used UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 33 Perform a full TX sequential reset after the PLL fully completes its reset procedure. After Assertion/Deassertion of TXPD[1:0] After the TXPD signal is deasserted, perform a full TX sequential reset. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 34 In either sequential mode or single mode, the RX reset state machine does not reset the PCS until RXUSERRDY goes High. Drive RXUSERRDY High after all clocks used by the application, including RXUSRCLK, are shown to be stable. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 35 RX PRBS Counter RXPCSRESETMASK[3] RX Adapt Reset RXPMARESETMASK[4] Reset = 1? = 1? RXRESETDONE High RX CDR PH Reset RXPMARESETMASK[5] = 1? RX CDR FR Reset RXPMARESETMASK[6] = 1? X20906-053118 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 36 This port is driven High and then deasserted to start a single mode reset on RX adaptation. The reset is not dependent on RXRESETMODE or RXPMARESETMASK setting. CH[0/1]_RXADCCALRESET Async Reserved. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 37 This port is driven High and then deasserted to start a single mode reset on the PRBS counter. The reset is not dependent on RXRESETMODE or RXPCSRESETMASK setting. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 38 Reserved. Represents the time duration to apply an RX PMA reset. Use the recommended value from the Wizard. Must be a non-zero value when RXPMARESETMASK[0] is High and GTRXRESET initiates the reset process. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 39 Reserved. Use the recommended value from the Wizard. RX_CDRPHASE_RESET_LOOP_ID [11:8] Reserved. Use the recommended value from the Wizard. RX_ADAPT_RESET_LOOP_ID [3:0] Reserved. Use the recommended value from the Wizard. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 40 3. All RXPMARESETMASK and RXPCSRESETMASK bits should be set to High. 4. GTRXRESET cannot be driven Low until the associated PLL is locked. 5. Ensure that GTPOWERGOOD is High before releasing PLLRESET and GTRXRESET. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 41 4. The guideline for this asynchronous GTRXRESET pulse width is one period of the reference clock. GTM Receiver Reset after GTRXRESET Pulse in Full Sequential Reset Figure 20: UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 42 RX PMA and RX RX rate change 2'b00 8’b11111111 4’b1111 RX parallel clock source reset RX PCS 2'b00 8’b00000000 4’b1111 After remote power up Entire RX 2'b00 8’b11111111 4’b1111 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 43 Perform a full RX sequential reset after the PLL fully completes its reset procedure. After Assertion/Deassertion of RXPD After the RXPD signal is deasserted, perform a full RX sequential reset. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 44 RX elastic buffer must be triggered after the recovered clock becomes stable. Refer to the UltraScale+ device device data sheets (see http:/ /www.xilinx.com/documentation) for successful CDR lock-to-data criteria. After an RX Elastic Buffer Error After an RX elastic buffer overflow or underflow, a sequential component reset targeting the RX PCS must be triggered to ensure correct behavior.

  • Page 45: Power Down

    Powering up/down multiple lanes in a Dual or multiple Duals affects the power supply regulation circuit (see Power Up/Down and Reset on Multiple Lanes). UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 46: Loopback

    Loopback testing can be used either during development or in deployed equipment for fault isolation. The traffic patterns used can be either application traffic patterns or specialized pseudo-random bit sequences. Each GTM transceiver has a built-in PRBS generator and checker. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 47: Dynamic Reconfiguration Port

    An enable signal (DRPEN), a read/write signal (DRPWE), and a ready/valid signal (DRPRDY) are the control signals that implement read and write operations, indicate operation completion, or indicate the availability of data. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 48 DRP transactions. Usage Model Write Operation The following figure shows the DRP write operation timing. New DRP operations can be initiated when DRPRDY is asserted. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 49 The following figure shows the DRP read operation timing. New DRP operations can be initiated when DRPY is asserted. DRP Read Timing Figure 23: DRPCLK DRPEN DRPRDY DRPWE DRPADDR DRPDI DRPDO X20219-052318 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 50: Digital Monitor

    Bit Field Description DMON_ENABLE Enables digital monitor for channel 0/1. DMON_SRC [2:1] Enables RX DMON path for channel 0/1. Must be set to 2’b00 when reading RX adaptation loops. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 51 Selector to monitor DFE and CTLE adaptation loops for channel 0/1. Value Adaptation Loop DFE Tap 1. 4’b0100 AGC frequency gain. 4’b0110 Low frequency gain. 4’b0111 High frequency gain. 4’b1000 Base line wander cancellation. 4’b1001 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 52 The DRP locations of the attributes are follows. Channel 0: • 0x082[0]: DMON_ENABLE • 0x082[2:1]: DMON_SRC • 0x033[14:12]: DEMONCON • 0x03B[15]: TESTSEL • 0x046[15:12]: DFELOOPSEL • 0x03f[15:12]: FFELOOPSEL Channel 1: • 0x282[0]: DMON_ENABLE UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 53 Chapter 2: Shared Features • 0x282[2:1]: DMON_SRC • 0x233[14:12]: DEMONCON • 0x23B[15]: TESTSEL • 0x246[15:12]: DFELOOPSEL • 0x23f[15:12]: FFELOOPSEL UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 54: Chapter 3: Transmitter

    The key elements within the GTM transceiver TX are: TX Interface TX FEC TX Buffer TX Pattern Generator TX Polarity Control TX Gray Encoder TX Pre-Coder TX Fabric Clock Output Control TX Configurable Driver UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 55: Tx Interface

    TX_DATA_WIDTH TX Data Width TX_INT_DATA_WI Encoding FEC Allowed? Datapath Encoding Selection DTH Encoding Selection PAM4 PAM4 PAM4 PAM4 The following figure shows how the TX data is transmitted. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 56 GTM_DUAL primitive and the TX line rate of the GTM transmitter. The following equation shows how to calculate the required rate for TXUSRCLK for all cases. Line Rate T XUSRCLK Rate = Internal Datapath Width UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 57 TX data width selection. 64: TXDATA[63:0]. 80: TXDATA[79:0]. 128: TXDATA[127:0]. 160: TXDATA[159:0]. 256: TXDATA[255:0]. TXUSRCLK Clock This port is used to provide a clock for the internal TX PCS datapath. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 58 TX interface width, otherwise this attribute is ignored. Use the recommended value from the Wizard: 0x0: Bypass TXUSRCLK flip-flops. 0x1: Enable TXUSRCLK flip-flops. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 59 BUFG_GT and BUFG_GT_SYNC), refer to the UltraScale Architecture Clocking Resources User Guide (UG572). 2. F TXUSRCLK2 TXUSRCLK 3. TXUSRCLK can be tied to 1’b0 if GEN_TXUSRCLK = 1’b1. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 60 1. For details about placement constraints and restrictions on clocking resources (such as BUFG_GT and BUFG_GT_SYNC), refer to the UltraScale Architecture Clocking Resources User Guide (UG572). 2. F TXUSRCLK2 TXUSRCLK UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 61 TXPROGDIVCLK. For example, in a multi-lane configuration of six GTM transceivers consisting of three contiguous Duals, one of the middle GTM transceivers in the middle Dual should be selected as the source of TXPROGDIVCLK. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 62 1. For details about placement constraints and restrictions on clocking resources (BUFG_GT, BUFG_GT_SYNC, etc.), refer to the UltraScale Architecture Clocking Resources User Guide (UG572). 2. F TXUSRCLK2 TXUSRCLK UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 63: Tx Fec

    The following table shows the TX FEC-related ports for the GTM dual. Table 32: TX FEC Ports Ports Clock Domain Description CH[0/1]_TXFECRESET Async Component reset port for TX FEC. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 64 4’b0001: 50G KP4 FEC, 50GAUI-1 format. 4’b0010: 100G KP4 FEC, 100GAUI-2 format. 4’b0101: 50G raw KP4 FEC without scrambling. 4’b1101: 50G raw KP4 FEC with scrambling. Others: Invalid. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 65 One channel of 100G Interlaken with KP4 FEC can be implemented as per the Interlaken Reed- Solomon Forward Error Correction Extension Protocol Definition. Transcoding should be disabled in the GTM Wizard IP for this mode. Line rates up to 58 Gb/s are possible. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 66: Tx Buffer

    Table 34: TX FIFO Data Width Conversion Scenarios PCS Parallel Clock (TXUSRCLK) PMA Parallel Clock (XCLK) Domain FEC Support Domain Data Width Data Width 64-bit 64-bit 80-bit 128-bit 128-bit 128-bit UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 67: Tx Pattern Generator

    PRBS patterns listed in the following table. Table 37: Supported PRBS Patterns Length of Name Polynomial Description Sequence PRBS-7 1 + x – 1 bits Used to test channels with 8B/10B. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 68 The error insertion function is also supported to verify link connection for jitter tolerance tests. When an inverted PRBS pattern is necessary, the CH[0/1]_TXPOLARITY signal is used to control polarity. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 69 When CH[0/1]_TXPRBSPTN is set to 4’b0000, this port does not affect CH[0/1]_TXDATA. CH[0/1]_TXQPRBSEN CH[0/1]_TXUSRCLK2 Reserved. This port must always be set to 1’b0. The following table defines the pattern generator attribute. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 70 CH[0/1]_TX_PCS_CFG0[4:0] = 0x0B for 160-bit data width mode. 3. Set CH[0/1]_TXPMARESETMASK = 0x0. 4. Toggle CH[0/1]_GTTXRESET High and Low. 5. Wait for CH[0/1]_TXRESETDONE to toggle High. 6. Set CH[0/1]_TXPMARESETMASK = 0x3. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 71: Tx Polarity Control

    Gray coding. By using Gray coding, only one bit error per symbol is made for incorrect decisions, thus reducing the bit-error rate by more than 33%. The following figure illustrates the differences between linear coding and Gray coding. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 72: Tx Pre-Coder

    GTM transmitters in UltraScale+ devices support pre-coding. Pre-coding can be used to reduce receiver decision feedback equalization (DFE) error propagation by reducing 1-tap burst error runs into two errors for every error event. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 73: Tx Fabric Clock Output Control

    The TX Clock Divider Control block has two main components: serial clock divider control, and parallel clock divider and selector control. The clock divider and selector details are illustrated in the following figure. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 74 By using the transceiver LCPLL, TX programmable divider, and BUFG_GT, CH[0/1]_TXPROGDIVCLK should be used as a clock source for the interconnect logic. The following tables show the programmable divider ports and attributes, respectively. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 75 This attribute is used during the TX programmable divider ratio selection. Set to 1’b1 to obtain the full rate of the divided clock. Set to 1’b0 to obtain the half rate of the divided clock. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 76 The attribute must be set to 1’b1 when the desired divider value is either 16.5, 33, 66, or 132. • For all other divider values, this should be set to 1’b0. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 77: Tx Configurable Driver

    • Differential voltage control • Two pre-cursor, and one post-cursor transmit pre-emphasis • Two modulation schemes: NRZ and PAM4 • Calibrated termination resistors UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 78 Port Description Domain CH[0/1]_TXDRVAMP[4:0] Input Async Driver swing control. The default is user specified. All listed values are in mV [4:0] 5’b00000 5’b00001 5’b00010 5’b00011 5’b00100 5’b00101 5’b00110 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 79 Allows the main cursor coefficients to be directly set if CH[0/1]_TX_DRV_CFG0[0] attribute is set to 1’b1. CH[0/1]_TXDRVAMP should be used together with CH[0/1]_TXEMPMAIN to achieve the desired TX output swing. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 80 5’b11000 –8.9 5’b11001 –9.2 5’b11010 Notes: The peak-to-peak differential voltage is defined when CH[0/1]_TXEMPPOST = 5’b00000, and CH[0/1]_TXEMPPRE2 = 4’b0000. Emphasis = 20log10(V ) = |20log10(V high high UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 81 –2.6 4’b1010 –2.9 4’b1011 Notes: The peak-to-peak differential voltage is defined when CH[0/1]_TXEMPPRE = 5’b00000, and CH[0/1]_TXEMPPOST = 4’b0000. Emphasis = 20log10(V ) = | high 20log10(V high UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 82 Implementation) and brought to the top of the design. CH[0/1]_TXCTLFIRDAT[5:0] Input Async Reserved. Use the recommended value from the Wizard CH[0/1]_TXMUXDCDEXHOLD Input Async Reserved. Use the recommended value from the Wizard. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 83 (UI). To program the GTM TX to a desired signal modulation mode, the user must configure the attribute TXMODSEL for CH0 or CH1. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 84: Chapter 4: Receiver

    RX Analog Front End RX Equalizer RX CDR RX Fabric Clock Output Control RX Margin Analysis RX Pre-Coder RX Gray Encoder RX Polarity Control RX Pattern Checker RX Buffer UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 85: Rx Analog Front End

    These ports represent pads. The location of these ports must be constrained (see Implementation) and brought to the top level of the design. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 86 4’b1100: 900 mV 4’b1101: 950 mV 4’b1110: 1000 mV 4’b1111: 1100 mV GTM Use Modes - RX Termination This section describes the GTM use modes with RX termination. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 87: Rx Equalizer

    The incoming signal first passes through the analog stage consisting of a CTLE and AGC stage. The signal is then digitized by the ADC, and passes through the Feed-Forward Equalizer (FFE) and Decision-Feedback-Equalizer (DFE), as shown in the following figure. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 88 DSP. The reset is not dependent on RXRESETMODE or RXPMARESETMASK setting. CH[0/1]_RXEQTRAINING Async Reserved. Tie to 1'b0. The following table defines the RX equalizer attributes. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 89 Adaptation freeze control. This bit must be enabled to freeze the loops selected in CH[0/1]_RX_APT_CFG27A, and CH[0/1]_RX_APT_CFG27B. If this bit is set to Low, all loops will be auto-adapting. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 90 Enable to freeze current FFE Tap HP3 adapt value. Enable to freeze current FFE Tap HP2 adapt value. Note Attribute CH[0/1]_RX_APT_CFG27A[0] must be enabled to freeze the enabled loops in CH[0/1]_RX_APT_CFG27B[15:0]. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 91 Adaptation override control. This bit must be enabled to override the loops selected in CH[0/1]_RX_APT_CFG28A, and CH[0/1]_RX_APT_CFG28B. If this this bit is set to low, all loops will be auto-adapting. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 92 (UI). To program the GTM RX to a desired signal modulation mode, the user must configure the attribute RXMODSEL for CH0 or CH1. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 93: Rx Cdr

    Ports and Attributes The following table defines the CDR ports. Table 52: CDR Ports Port Clock Domain Description CH[0/1]_RXCDROVRDEN Async Reserved. Use the recommended value from the Wizard. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 94: Rx Fabric Clock Output Control

    The RX Clock Divider Control block has two main components: serial clock divider control, and parallel clock divider and selector control. The clock divider and selector details are illustrated in the following figure. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 95 By using the transceiver LCPLL, RX programmable divider, and BUFG_GT, CH[0/1]_RXPROGDIVCLK should be used as a clock source for the interconnect logic. The following tables show the programmable divider ports and attributes, respectively. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 96 The attribute must be set to 1’b0 when the desired divider value is either 16.5, 33, 66, or 132. • For all other divider values, this should be set to 1’b1. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 97 Valid RX programmable divider ratios are: 6'b011000: 16.5 (33) 6'b000000: 33 (66) 6'b000010: 66 (132) Ports and Attributes The following table defines the ports required for TX fabric clock output control. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 98: Rx Margin Analysis

    Sampled Eye Diagram for (a) PAM4 and (b) NRZ Modulation Figure 42: UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 99: Rx Pre-Coder

    Gray coding. By using Gray coding, only one bit error per symbol is made for incorrect decisions, thus reducing the bit-error rate by more than 33%. Table 58 illustrates the differences between linear and Gray Coding. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 100: Rx Polarity Control

    CH0_RXPOLARITY and CH1_RXPOLARITY input, which is driven High from the interconnect logic interface to invert polarity. Ports and Attributes The following table defines the ports required for RX polarity control. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 101: Rx Pattern Checker

    X20928-053118 Ports and Attributes The following table defines the pattern checker ports. Table 60: Pattern Checker Ports Port Clock Domain Description CH[0/1]_RXPRBSCSCNTRST CH[0/1]_RXUSRCLK2 Reset the PRBS error counter. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 102 This allows synchronous and asynchronous jitter tolerance testing without worrying about data clock domain crossing. When this attribute is set to 1b’0, CH[0/1]_TXPRBSINERR is forced onto the TX PRBS. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 103 The GTM RX pattern checker works for all supported data widths. However, 80-bit or 160-bit RX fabric data width in PAM4 mode requires additional steps. Other data widths do not require any additional steps. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 104: Rx Buffer

    (RXUSRCLK). To receive data, the RX buffer provides data width conversion between these clock domains when necessary, depending on the operating data width and encoding mode. The following figure shows the RX datapath clock domains. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 105 Description CH[0/1]_RXBUFSTATUS[1:0] RXUSRCLK RX buffer status: Bit[1]: FIFO overflow status. A value of 1 indicates FIFO overflow. Bit[0]: FIFO underflow status. A value of 1 indicates FIFO underflow. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 106: Rx Fec

    58 Gb/s channel, or as a raw data stream (one virtual lane) with optional PN scrambling for backplane operations. The general principle of operation of the FEC is the same whichever mode is chosen. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 107 Slice 0 corrected codeword count increment. FECRX1CORRCWINC CH1_RXUSRCLK2 Slice 1 corrected codeword count increment. FECTRXLN0LOCK CH0_RXUSRCLK2 Lane 0 lock status. FECTRXLN1LOCK CH0_RXUSRCLK2 Lane 1 lock status. FECTRXLN2LOCK CH1_RXUSRCLK2 Lane 2 lock status. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 108 When configured in 100G mode (combined slice 0 and slice 1 operation), CH0_RXUSRCLK and CH1_RXUSRCLK must be driven from the same source with low skew. The same applies to CH0_RXUSRCLK2 and CH1_RXUSRCLK2. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 109 4’b1101: 50G raw KP4 FEC with scrambling. Others: Invalid. FEC_CFG3 16-bit Reserved. Bit Name Address Description FEC_RX0_BYPASS_CORRECTION FEC RX slice 0 error correction select: 1’b0: Error correct enabled. 1’b1: Error correct disabled. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 110 BER is low enough that full error correction is not required. The following table lists the valid RS-FEC operating sub-modes. When configured in 2x50G FEC mode, the sub- mode can be set independently for each slice. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 111 This signal is not active when the FEC is configured in 50G raw mode. In 100G mode, CH1_RXDATAISAM should be ignored. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 112 When the FEC is enabled in any mode other than the 50G raw modes, these signals are ignored. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 113: Rx Interface

    Table 69: RX Interface Datapath Configuration RX Internal Encod RX_DATA_WIDTH RX Data Width RX_INT_DATA_WID Datapath Allowed? Encoding Selection TH Encoding Selection PAM4 The following figure shows the RX data received. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 114 GTM_DUAL primitive and the RX line rate of the GTM transmitter. The following equation shows how to calculate the required rate for RXUSRCLK for all cases. Line Rate RXUSRCLK Rate Internal Datapath Width UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 115 The bus for receiving data. The width of this port is equal to RX data width selection. RX data width selection: 64: RXDATA[63:0] 80: RXDATA[79:0] 128: RXDATA[127:0] 160: RXDATA[159:0] 256: RXDATA[255:0] UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 116 RX interface width, otherwise this attribute is ignored. Use the recommended value from the Wizard. 0x0: Bypass RXUSRCLK flip-flops. 0x1: Enable RXUSRCLK flip-flops. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 117: Chapter 5: Board Design Guidelines

    MGTAVTT. Refer to the package pin definitions to identify the location of the power supply group for a specific GTM transceiver Dual. The nominal voltage is 1.2 VDC. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 118 Dual. The nominal voltage is 0.9 VDC or 0.85 VDC depending on the speed grade. See the UltraScale+ device data sheets (see http://www.xilinx.com/documentation) for details. The following figure shows the external power supply connectins with the GTM transceivers. GTM Transceivers External Power Supply Connections...
  • Page 119 UltraScale+ device data sheets (see http:/ /www.xilinx.com/documentation). If an entire power supply group (PSG) is not used by any Duals, MGTAVTTRCAL and MGTRREF should be tied to ground. See...

  • Page 120: Reference Clock

    UltraScale+ Device Transceiver Power Supply Groups and RCAL Master Figure 48: Reference Clock This section focuses on the selection of the reference clock source or oscillator. An oscillator is characterized by: • Frequency range UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 121 This figure is provided to show the contrast to the differential clock input voltage swing calculation shown in Figure 50, as used in the GTM transceiver portion of the UltraScale+ device data sheets (see http:/ /www.xilinx.com/documentation). Single-Ended Clock Input Voltage Swing, Peak-to-Peak Figure 49: MGTREFCLKP Single-Ended Voltage MGTREFCLKN...

  • Page 122: Gtm Transceiver Reference Clock Checklist

    4/5 of MGTAVCC, or nominal 0.8V for UltraScale FPGAs. The common mode voltage for UltraScale+ FPGAs is MGTAVCC, or nominal 0.9V. See the UltraScale and UltraScale+ device data sheets (see http:/ /www.xilinx.com/documentation) for exact specifications. GTM Transceiver Board Design Guidelines Figure 52: 50Ω...

  • Page 123: Reference Clock Interface

    GTM Transceiver LVDS Oscillator Reference Clock Input Buffer X20934-053118 LVPECL The following figure shows how an LVPECL oscillator is connected to a reference clock input of a GTM transceiver. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 124: Ac Coupled Reference Clock

    UltraScale+ device data sheets (see http:/ / www.xilinx.com/documentation). AC Coupled Reference Clock AC coupling of the oscillator reference clock output to the GTM transceiver Dual reference clock inputs serves multiple purposes: •...

  • Page 125: Unused Reference Clocks

    PCB. The signal levels are comparable to those of LVDS after the DC blocking capacitors. See the UltraScale+ device data sheets (see http:/ /www.xilinx.com/documentation) for output levels. Reference Clock Power The GTM transceiver reference clock input circuit is powered by MGTAVCC. Excessive noise on this supply has a negative impact on the performance of any GTM transceiver Dual that uses the reference clock from this circuit.
  • Page 126 UltraScale+ device data sheets (see http:/ /www.xilinx.com/ documentation). Use the Xilinx Power Estimator (XPE) tool to calculate the amount of power required for the transceivers in your application. Power Supply Regulators Normally, the GTM transceiver analog voltage supplies have local power supply regulators that provide a final stage of voltage regulation.
  • Page 127 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 128 GTM transceiver Duals. These capacitors in the package also aid in maintaining a low-impedance, high-frequency path between the power supply, MGTAVCC, MGTVCCAUX, VCCINT_GT or MGTAVTT, and GND. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 129: Pcb Design Checklist

    • Reference clock oscillator output must comply with the minimum and maximum input amplitude requirements for these input pins. See the UltraScale+ device data sheets (see http://www.xilinx.com/documentation). When configured as an output: • Use AC coupling capacitors for connection to receiving device.
  • Page 130 MGTAVTTRCAL. Also, the DC resistance of the PCB trace should be limited to less than 0.5Ω. • Termination Resistor Calibration Circuit. • If an entire PSG is not used by any Duals, tie MGTRREF to ground. UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 131 If all of the Duals in a power supply group are not used, the associated power pins can be left unconnected or tied to GND. • For power consumption, refer to the Xilinx Power Estimator (XPE) at www.xilinx.com/power. MGTMAVTT[N] •...
  • Page 132 • For UltraScale+ FPGAs, the nominal voltage is 0.85 VDC or 0.9 VDC. • See the UltraScale+ device data sheets (see http://www.xilinx.com/documentation) for power supply voltage tolerances. • Many packages have multiple groups of power supply connections in the package for VCCINT_GT.

  • Page 133: Appendix A: Drp Address Map Of The Gtm Transceiver In Ultrascale+ Fgpas

    CH0_TX_ANA_CFG0 [15:0] 0–65535 0–65535 0x010 [15:0] CH0_RX_ANA_CFG0 [15:0] 0–65535 0–65535 0x011 [15:0] CH0_RX_ANA_CFG1 [15:0] 0–65535 0–65535 0x012 [15:0] CH0_RX_PAD_CFG0 [15:0] 0–65535 0–65535 0x013 [15:0] CH0_RX_PAD_CFG1 [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 134 CH0_RX_APT_CFG9A [15:0] 0–65535 0–65535 0x035 [15:0] CH0_RX_APT_CFG9B [15:0] 0–65535 0–65535 0x036 [15:0] CH0_RX_APT_CFG10A [15:0] 0–65535 0–65535 0x037 [15:0] CH0_RX_APT_CFG10B [15:0] 0–65535 0–65535 0x038 [15:0] CH0_RX_APT_CFG11A [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 135 CH0_RX_APT_CFG26B [15:0] 0–65535 0–65535 0x05a [15:0] CH0_RX_APT_CFG27A [15:0] 0–65535 0–65535 0x05b [15:0] CH0_RX_APT_CFG27B [15:0] 0–65535 0–65535 0x05c [15:0] CH0_RX_DSP_CFG [15:0] 0–65535 0–65535 0x064 [15:0] CH0_RX_CAL_CFG2A [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 136 CH0_TX_PCS_CFG17 [15:0] 0–65535 0–65535 0x095 [15:0] CH0_A_CH_CFG0 [15:0] 0–65535 0–65535 0x096 [15:0] CH0_A_CH_CFG1 [15:0] 0–65535 0–65535 0x097 [15:0] CH0_A_CH_CFG2 [15:0] 0–65535 0–65535 0x098 [15:0] CH0_A_CH_CFG3 [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 137 A_SDM_DATA_CFG1 [15:0] 0–65535 0–65535 0x0be [15:0] PLL_CRS_CTRL_CFG0 [15:0] 0–65535 0–65535 0x0bf [15:0] PLL_CRS_CTRL_CFG1 [15:0] 0–65535 0–65535 0x0c0 [15:0] A_CFG [15:0] 0–65535 0–65535 0x0c1 [15:0] SAP_CFG0 [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 138 BIAS_CFG3 [15:0] 0–65535 0–65535 0x162 [15:0] BIAS_CFG4 [15:0] 0–65535 0–65535 0x163 [15:0] BIAS_CFG5 [15:0] 0–65535 0–65535 0x164 [15:0] BIAS_CFG6 [15:0] 0–65535 0–65535 0x165 [15:0] BIAS_CFG7 [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 139 CH1_RX_APT_CTRL_CFG3 [15:0] 0–65535 0–65535 0x222 [15:0] CH1_RX_APT_CFG0A [15:0] 0–65535 0–65535 0x223 [15:0] CH1_RX_APT_CFG0B [15:0] 0–65535 0–65535 0x224 [15:0] CH1_RX_APT_CFG1A [15:0] 0–65535 0–65535 0x225 [15:0] CH1_RX_APT_CFG1B [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 140 CH1_RX_APT_CFG18A [15:0] 0–65535 0–65535 0x247 [15:0] CH1_RX_APT_CFG18B [15:0] 0–65535 0–65535 0x248 [15:0] CH1_RX_APT_CFG19A [15:0] 0–65535 0–65535 0x249 [15:0] CH1_RX_APT_CFG19B [15:0] 0–65535 0–65535 0x24a [15:0] CH1_RX_APT_CFG20A [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 141 CH1_RX_PCS_CFG1 [15:0] 0–65535 0–65535 0x282 [15:0] CH1_RX_MON_CFG [15:0] 0–65535 0–65535 0x283 [15:0] CH1_TX_PCS_CFG0 [15:0] 0–65535 0–65535 0x284 [15:0] CH1_TX_PCS_CFG1 [15:0] 0–65535 0–65535 0x285 [15:0] CH1_TX_PCS_CFG2 [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...
  • Page 142 CH1_RST_LP_CFG0 [15:0] 0–65535 0–65535 0x2aa [15:0] CH1_RST_LP_CFG1 [15:0] 0–65535 0–65535 0x2ab [15:0] CH1_RST_LP_CFG2 [15:0] 0–65535 0–65535 0x2ac [15:0] CH1_RST_LP_CFG3 [15:0] 0–65535 0–65535 0x2ad [15:0] CH1_RST_LP_CFG4 [15:0] 0–65535 0–65535 UG581 (v1.0) January 4, 2019 www.xilinx.com Send Feedback Virtex UltraScale+ GTM Transceivers...

  • Page 143: Appendix B: Additional Resources And Legal Notices

    • On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •...

  • Page 144: Please Read: Important Legal Notices

    IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...
  • Page 145 Appendix B: Additional Resources and Legal Notices Copyright © Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

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