Chapter 2: Shared Features; Reference Clock Input/Output Structure - Xilinx Virtex UltraScale+ FPGAs User Manual

Shared Features

Reference Clock Input/Output Structure

The reference clock structure in the GTM transceiver supports two modes of operation: input
mode and output mode. In the input mode of operation, your design provides a clock on the
dedicated reference clock I/O pins that are used to drive the LCPLL. In the output mode of
operation, the recovered clocks (RXRECCLK0 and RXRECCLK1) from any of the two channels
within the same Dual can be routed to the dedicated reference clock I/O pins. This output clock
can then be used as the reference clock input at a different location. The mode of operation
cannot be changed during run time.
Input Mode
The reference clock input mode structure is illustrated in the following figure. The input is
terminated internally with 50Ω on each leg to MGTAVCC. The reference clock is instantiated in
software with the IBUFDS_GTM software primitive. The ports and attributes controlling the
reference clock input are tied to the IBUFDS_GTM software primitive.
MGTAVCC
GTREFCLKP
GTREFCLKN
CEB
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Reference Clock Input Structure
Figure 4:
I
Nominal
50Ω
IB
Nominal
50Ω
IBUFDS_GTM
+
- MGTAVCC
Reserved
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Chapter 2: Shared Features

Chapter 2
To GTREFCLK or
GTM_DUAL
2'b00
To
/2 2'b01
HROW
1'b0
2'b10
2'b11
REFCLK_HROW_CK_SEL
X20917-061418
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O
ODIV2
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