Xilinx 7 Series User Manual page 143

Table 4-11: CDR Ports (Cont'd)
Port
RXOSINTSTROBE
RXOSINTHOLD
RXOSINTTESTOVRDEN
RXOSINTSTARTED
RXOSINTSTROBESTARTED
RXOSINTDONE
Table 4-12
Table 4-12: CDR Attributes
CFOK_CFG
CFOK_CFG2
CFOK_CFG3
RXCDR_CFG
RXCDR_LOCK_CFG
RXCDR_HOLD_DURING_EIDLE
RXCDR_FR_RESET_ON_EIDLE
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Dir Clock Domain
In Async
In Async
In Async
Out Async
Out Async
Out Async
defines the CDR related attributes.
Attribute
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Description
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Type
43-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
7-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
7-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
83-bit Hex CDR configuration. The recommended
value from the 7 Series FPGAs
Transceivers Wizard should be used.
6-bit Binary CDR Lock loop configuration. The
recommended value from the 7 Series
FPGAs Transceivers Wizard should be
used.
Binary Enables the CDR to hold its internal states
during an optional PCI Express reset
sequence during electrical idle.
Binary Enables automatic reset of the CDR
frequency during the optional PCI Express
reset sequence during electrical idle.
RX CDR
Description
143
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