Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual
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Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual

Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual

Characterization kit ibert, vivado design suite
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Kintex UltraScale FPGA
KCU1250
Characterization Kit
IBERT
Getting Started Guide
Vivado Design Suite
UG1061 (v2017.4) December 20, 2017

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Summary of Contents for Xilinx Kintex UltraScale FPGA KCU1250

  • Page 1 Kintex UltraScale FPGA KCU1250 Characterization Kit IBERT Getting Started Guide Vivado Design Suite UG1061 (v2017.4) December 20, 2017...

  • Page 2: Revision History

    Board power on was added to step 3, page 13. Updated Figure 2-2, Figure 2-4, and Figure 2-8. 04/27/2015 2015.1 Initial Xilinx release. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...

  • Page 3: Table Of Contents

    Xilinx Resources ........

  • Page 4: Chapter 1: Kcu1250 Ibert Getting Started Guide

    Connecting the GTH Transceivers and Reference Clocks Starting the SuperClock-2 Module Configuring the FPGA Setting Up the Vivado Design Suite Viewing GTH Transceiver Operation Closing the IBERT Demonstration KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...

  • Page 5: Requirements

    • Xilinx Vivado Design Suite 2017.4 • PC with a version of Windows supported by Xilinx Vivado Design Suite Setting Up the KCU1250 Board This section describes how to set up the KCU1250 board. The KCU1250 board can be damaged by electrostatic discharge (ESD). Follow...

  • Page 6: Extracting The Project Files

    The Vivado Design Suite BIT files required to run the IBERT demonstrations are located in rdf0352-kcu1250-ibert-2017-4.zip on the SD card provided with the KCU1250 board. The BIT files are also available online at Kintex UltraScale FPGA KCU1250 Characterization Kit documentation.

  • Page 7: Running The Gth Ibert Demonstration

    Quad 131 and Quad 132 are not available on the XCKU040 device. Note: X-Ref Target - Figure 1-1 QUAD_224 QUAD_225 QUAD_226 QUAD_227 QUAD_228 QUAD_131 QUAD_132 Figure 1-1: GTH Quad Locations KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 8 LVDS clock output from the Si570 programmable oscillator on the clock module. The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the Note: SuperClock-2 module. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 9 X-Ref Target - Figure 1-5 Figure 1-5: Bulls Eye Connector Attached to Quad 224 KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 10 To ensure good connectivity, it is recommended that the adapters be secured with a RECOMMENDED: wrench; however, do not over-tighten the SMAs. X-Ref Target - Figure 1-6 Figure 1-6: SMA F-F Adapter KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 11 KCU1250 board with the cable connections required for the Quad 224 GTH IBERT demonstration. X-Ref Target - Figure 1-8 Figure 1-8: Cable Connections for Quad 224 GTH IBERT Demonstration KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 12 Outputs from either source can be used to drive the transceiver reference clocks. To start the SuperClock-2 module: 1. Configure the SuperClock-2 module using the Xilinx XC7Z010CLG225 Zynq-7000 AP SoC System Controller command line, which can be accessed through a serial...
  • Page 13 5. Open a serial communication terminal application on the host computer, for example “Hyper Terminal”. 6. Connect to the port number associated with the enhanced COM port of the Silicon Lab USB-UART Bridge. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 14 11. Select option 2 Free-Run using XA-XB crystal operating mode when prompted. Configuring the FPGA The Xilinx Zynq-7000 AP SoC XC7Z010CLG225 System Controller includes a System Integrated Configuration Engine (System ICE) option. The System ICE can be used to configure the FPGA, in 8-bit SMAP configuration mode, using one of the *.bit files provided on the SD card.
  • Page 15 4. Select option (0) to configure the FPGA with the Quad 224 IBERT example design. Press Enter and review the terminal for configuration progress: Enter a Bitstream number (0-15): Info: xilinx.sys opened Info: Opening rev_1/set0/config.def Info: Configuration definition file "rev_1/set0/config.def"...
  • Page 16 U80 (the Digilent USB JTAG configuration port on the KCU1250 board (Figure 1-13)). X-Ref Target - Figure 1-13 Figure 1-13: USB-UART Connector KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 17 2. Start the Vivado Design Suite on the host computer and click Flow > Open Hardware Manager (highlighted in Figure 1-14). X-Ref Target - Figure 1-14 Figure 1-14: Vivado Design Suite, Open Hardware Manager KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 18 X-Ref Target - Figure 1-15 Figure 1-15: Open a New Hardware Manager 4. In the Hardware Server Settings window, select Local server (target is on local machine). Click Next. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 19 Links can also be created manually in the Links window by right-clicking and selecting Create Links or by clicking the Create Links button (Figure 1-17). KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 20 Chapter 1: KCU1250 IBERT Getting Started Guide X-Ref Target - Figure 1-17 Figure 1-17: Serial I/O Analyzer – Create Links KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 21 MGT_X0Y1/TX (xcku040_0/Quad_224) to MGT_X0Y1/RX (xcku040_0/Quad_224) ° MGT_X0Y2 /TX (xcku040_0/Quad_224) to MGT_X0Y2/RX (xcku040_0/Quad_224) ° MGT_X0Y3/TX (xcku040_0/Quad_224) to MGT_X0Y3/RX (xcku040_0/Quad_224) ° X-Ref Target - Figure 1-18 Figure 1-18: Create Links Window KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 22 Increase the TX differential swing of the transceiver (to compensate for any loss due to PCB process variation). • Click the respective TX Reset button followed by BERT Reset. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 23 To close the IBERT demonstration: 1. Close the Vivado Design Suite by selecting File > Exit. 2. Place the main power switch SW1 in the OFF position. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...

  • Page 24: Chapter 2: Creating The Gth Ibert Core

    Programming and Debugging (UG908) [Ref 1. Start the Vivado Design Suite. 2. In the Vivado Design Suite window, click Manage IP (highlighted in Figure 2-1) and select New IP Location. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 25 Chapter 2: Creating the GTH IBERT Core X-Ref Target - Figure 2-1 Figure 2-1: Vivado Design Suite Initial Window KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 26 Use the drop-down menu items to filter the devices. Select the xcku040-ffva1156-3-e device (see Figure 2-2). Click OK. X-Ref Target - Figure 2-2 Figure 2-2: Select Device KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 27 Target simulator, Mixed for Simulator language, and a directory to save the customized IP (Figure 2-3). Click Finish. Make sure the directory name does not include spaces. Note: X-Ref Target - Figure 2-3 Figure 2-3: Manage IP Settings KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 28 5. In the IP Catalog window, expand the Debug & Verification folder, expand the Debug folder, and double-click IBERT UltraScale GTH (Figure 2-4). X-Ref Target - Figure 2-4 Figure 2-4: IP Catalog KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 29 12.5 Gbps. Change Refclk (MHz) to 125. Keep defaults for other fields (Figure 2-5). X-Ref Target - Figure 2-5 Figure 2-5: Customize IP – Protocol Definition KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 30 QUAD_224 to select Custom 1/12.5 Gb/s and select MGTREFCLK0 224 from the REFCLK Selection menu (Figure 2-6). X-Ref Target - Figure 2-6 Figure 2-6: Customize IP – Protocol Selection KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 31 P Package Pin (the FPGA pins to which the system clock is connected), and make sure the Frequency (MHz) is set to 300 (Figure 2-7). Click OK. X-Ref Target - Figure 2-7 Figure 2-7: Customize IP - Clock Settings KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 32 2-8). Specify a location to save the design, click OK, and the example design launches in a new Vivado Design Suite window. X-Ref Target - Figure 2-8 Figure 2-8: Open IP Example Design KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 33 10. In the Sources window, Design Sources should now show the IBERT design example (Figure 2-9). X-Ref Target - Figure 2-9 Figure 2-9: Design Sources File Hierarchy KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 34 Chapter 2: Creating the GTH IBERT Core 11. Click Run Synthesis from the Flow Navigator to synthesize the design (Figure 2-10). X-Ref Target - Figure 2-10 Figure 2-10: Run Synthesis KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 35 13. When the implementation is done, an Implementation Completed window opens. Select Generate Bitstream and click OK (Figure 2-12). X-Ref Target - Figure 2-12 Figure 2-12: Implementation Completed KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...
  • Page 36 14. When the Bitstream Generation Completed dialog window appears, click Cancel (Figure 2-13). X-Ref Target - Figure 2-13 Figure 2-13: Bitstream Generation Complete 15. Navigate to the ...\ibert_ultrascale_gth_0_example\ ibert_ultrascale_gth_0_example.runs\impl_1 directory to locate the generated bitstream. KCU1250 IBERT Getting Started Guide Send Feedback UG1061 (v2017.4) December 20, 2017 www.xilinx.com...

  • Page 37: Appendix A: Warranty

    Customer. For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products.

  • Page 38: Appendix B: Additional Resources And Legal Notices

    Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® IDE, select Help > Documentation and Tutorials.

  • Page 39: References

    Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 40 © Copyright 2015–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

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