Xilinx 7 Series User Manual page 298

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
15:0
0064
12:8
0065
15:0
0066
3
0068
1
0068
0
0068
14:0
0069
15:13
006A
4:0
006A
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R/W Attribute Name
R/W TXPH_CFG
R/W TXPH_MONITOR_SEL
R/W RX_BIAS_CFG
R/W RXOOB_CLK_CFG
R/W TX_CLKMUX_EN
R/W RX_CLKMUX_EN
R/W TERM_RCAL_CFG
R/W TERM_RCAL_OVRD
R/W TX_CLK25_DIV
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Attribute Attribute
Bits Encoding
15:0 0-65535
4:0 0-31
15:0 0-65535
PMA
0
FABRIC
0 0-1
0 0-1
14:0 0-32767
2:0 0-7
1
2
3
4
5
6
7
8
9
10
11
4:0 12
13
14
15
16
17
18
19
20
21
22
23
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0-65535
0-31
0-65535
0
1
0-1
0-1
0-32767
0-7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22