Xilinx 7 Series User Manual page 269

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
9:7
0012
6:0
0012
14:9
0013
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W SATA_BURST_VAL
R/W RXOOB_CFG
R/W SAS_MIN_COM
www.xilinx.com
Attribute Attribute
Bits Encoding
2:0 0-7
6:0 0-127
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5:0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Send Feedback
DRP
Encoding
0-7
0-127
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
269