Xilinx 7 Series User Manual page 133

Also, the attribute PCS_RSVD_ATTR[8] should be set to 1'b1. The OOB circuit has two possible
sources from which it can receive a clock, as shown in
X-Ref Target - Figure 4-6
The attribute RXOOB_CLK_CFG controls the source of oobclk. Setting RXOOB_CLK_CFG to
1'b0 selects the reference clock connected to PLL0 or PLL1. RXSYSCLKSEL controls which of
the two reference clocks is selected. Setting RXOOB_CLK_CFG to 1'b0 selects an alternative
clock source from SIGVALIDCLK. A divided down reference clock can be connected to the
SIGVALIDCLK port pin, providing an alternative clock for the OOB circuit.
The divided down clock(s) requires no special phase relationships between other clocks in the
SERDES. However, there is a requirement of a 50% duty cycle.
method for clock division.
REFCLK.
X-Ref Target - Figure 4-7
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
RXSYSCLKSEL
(Port)
PLL0REFCLK
0
RXPLLREFCLK_DIV1
1
PLL1REFCLK
SIGVALIDCLK
Figure 4-6: Clocking Mechanism for the OOB Detect Circuit
Figure 4-7 shows how a simple toggle flip-flop can be used to divide the
Clk
Input
Figure 4-7: Toggle Flip-Flop to Divide REFCLK
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RX Out-of-Band Signaling
Figure 4-6.
0
oobclk
1
(Port)
RXOOB_CLK_CFG
(Attribute)
UG482_c4_106_021113
Figure 4-7
Clk/2
D
Q
Output
UG476_c4_107_071712
Send Feedback
OOB
and Figure 4-8 show the
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