Xilinx 7 Series User Manual page 55

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7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 2-20:
"DRP wr" denotes the function of performing a DRP write to addr 9'h011. The exact DRP
transaction is not shown.
The sequence of events in Figure 2-20
When the user wants to trigger RX reset upon configuration, assert and release
PLL[0/1]RESET while GTRXRESET is kept asserted. The assertion of GTRXRESET causes
RXPMARESETDONE to go Low.
Issue a DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9'h011, set bit[11] to
1'b0.
a. To ensure only bit[11] of DRPADDR 9'h011 is modified, it is best to perform a
read-modify-write function.
Upon DRP write completion, the user can set and hold GTRXRESET Low as desired. The user
can extend the assertion of GTRXRESET, as long as GTRXRESET is held High until the DRP
write is completed.
Wait for the falling edge of RXPMARESETDONE.
Issue a DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9'h011, restoring the
original setting for bit[11]. The completion of this DRP write must occur before
RXPMARESETDONE switches from Low to High. RXPMARESETDONE stays Low for a
minimum of 0.66 µs.
GTRXRESET should be driven with an output of a register to avoid glitches.
RXPMARESET_TIME should be set to 5'h3. This should be the default setting.
The sequence above will simulate correctly if SIM_RESET_SPEEDUP is set to FALSE. If
SIM_RESET_SPEEDUP is set to TRUE, the above sequence should be bypassed.
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Reset and Initialization
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