Xilinx 7 Series User Manual page 287

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
8:6
0019
5
0019
4:0
0019
15:8
001A
7:0
001A
12:1
001B
0
001B
15
001C
14
001C
5
001C
2:0
001C
14
001E
12:0
0024
15:14
002A
13:0
002A
15:0
002B
15:0
002C
15:0
002D
15:0
002E
15:0
002F
15:0
0030
15:0
0031
15:0
0032
15:0
0033
15:0
0034
15:0
0035
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W TX_EIDLE_ASSERT_DELAY
R/W TX_LOOPBACK_DRIVE_HIZ
R/W TX_DRIVE_MODE
R/W PD_TRANS_TIME_TO_P2
R/W PD_TRANS_TIME_NONE_P2
R/W PD_TRANS_TIME_FROM_P2
R/W PCS_PCIE_EN
R/W TXBUF_RESET_ON_RATE_CHANGE
R/W TXBUF_EN
R/W TXGEARBOX_EN
R/W GEARBOX_MODE
R/W RXLPM_HOLD_DURING_EIDLE
R/W RX_OS_CFG
R/W RXLPM_LF_CFG
R/W RXLPM_HF_CFG
R/W RXLPM_LF_CFG
R/W ES_QUALIFIER
R/W ES_QUALIFIER
R/W ES_QUALIFIER
R/W ES_QUALIFIER
R/W ES_QUALIFIER
R/W ES_QUAL_MASK
R/W ES_QUAL_MASK
R/W ES_QUAL_MASK
R/W ES_QUAL_MASK
R/W ES_QUAL_MASK
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Attribute Attribute
Bits Encoding
2:0 0-7
FALSE
0
TRUE
DIRECT
0
PIPE
7:0 0-255
7:0 0-255
11:0 0-4095
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
2:0 0-7
0 0-1
12:0 0-8191
17:16 0-3
13:0 0-16383
15:0 0-65535
15:0 0-65535
31:16 0-65535
47:32 0-65535
63:48 0-65535
79:64 0-65535
15:0 0-65535
31:16 0-65535
47:32 0-65535
63:48 0-65535
79:64 0-65535
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DRP
Encoding
0-7
0
1
0
1
0-255
0-255
0-4095
0
1
0
1
0
1
0
1
0-7
0-1
0-8191
0-3
0-16383
0-65535
0-65535
0-65535
0-65535
0-65535
0-65535
0-65535
0-65535
0-65535
0-65535
0-65535
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