Xilinx 7 Series User Manual page 297

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0053
15:12
(Cont'd)
9:0
0053
15:0
0054
15:0
0055
12:8
0057
5:0
0057
7
0059
6
0059
9
005A
8
005A
10:8
005D
7
005D
6
005D
5:4
005D
3:2
005D
1:0
005D
15:14
005E
15:0
0060
7:0
0061
15:0
0062
15:0
0063
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W CHAN_BOND_MAX_SKEW
R/W CHAN_BOND_SEQ_2_4
R/W RXDLY_TAP_CFG
R/W RXDLY_CFG
R/W RXPH_MONITOR_SEL
R/W RX_DDI_SEL
R/W TX_XCLK_SEL
R/W RXBUF_EN
R/W TXOOB_CFG
R/W LOOPBACK_CFG
R/W TXPI_CFG5
R/W TXPI_CFG4
R/W TXPI_CFG3
R/W TXPI_CFG2
R/W TXPI_CFG1
R/W TXPI_CFG0
R/W SATA_PLL_CFG
R/W TXPHDLY_CFG
R/W TXPHDLY_CFG
R/W TXDLY_CFG
R/W TXDLY_TAP_CFG
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Attribute Attribute
Bits Encoding
7
8
9
10
3:0
11
12
13
14
9:0 0-1023
15:0 0-65535
15:0 0-65535
4:0 0-31
5:0 0-63
TXOUT
0
TXUSR
FALSE
0
TRUE
0 0-1
0 0-1
2:0 0-7
0 0-1
0 0-1
1:0 0-3
1:0 0-3
1:0 0-3
VCO_3000MHZ
1:0
VCO_1500MHZ
VCO_750MHZ
15:0 0-65535
23:16 0-255
15:0 0-65535
15:0 0-65535
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DRP
Encoding
7
8
9
10
11
12
13
14
0-1023
0-65535
0-65535
0-31
0-63
0
1
0
1
0-1
0-1
0-7
0-1
0-1
0-3
0-3
0-3
0
1
2
0-65535
0-255
0-65535
0-65535
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