Xilinx 7 Series User Manual page 42

Chapter 2: Shared Features
The initializing TX must use GTTXRESET in sequential mode. Activating the GTTXRESET input
can automatically trigger a full asynchronous TX reset. The reset state machine executes the reset
sequence, as shown in
operation, when needed, sequential mode allows the user to reset TX from activating
TXPMARESET and continue the reset state machine until TXRESETDONE transitions from Low
to High.
The TX reset state machine does not reset the PCS until TXUSERRDY is detected High. The user
should drive TXUSERRDY High after these conditions are met:
1.
2.
X-Ref Target - Figure 2-13
Ports and Attributes
Table 2-14
Table 2-14: TX Initialization and Reset Ports
GTTXRESET
TXPMARESET
42
Send Feedback
Figure 2-13, covering the whole TX PMA and TX PCS. During normal
All clocks used by the application including TXUSRCLK/TXUSRCLK2 are shown as stable or
locked when the PLL or MMCM is used.
The user interface is ready to transmit data to the GTP transceiver.
TXPMARESET
WAIT Until
High
TXPMARESET
From High to Low
TXPCSRESET
WAIT Until
High
TXPCSRESET
From High to Low
Figure 2-13: GTP Transceiver TX Reset State Machine Sequence
lists ports required by TX initialization process.
Port Dir
In
In
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WAIT Until
GTTXRESET From
High to Low
TXPMARESET
Process
TXPCSRESET
Process
TXRESETDONE
High
Clock Domain
Async This port is driven High and then deasserted to
start the full TX reset sequence.
Async This port is used to reset the TX PMA. It is
driven High and then deasserted to start the TX
PMA reset process. In sequential mode,
activating this port resets both the TX PMA and
the TX PCS.
7 Series FPGAs GTP Transceivers User Guide
GTTXRESET
High
Sequence Mode & TXUSERRDY
UG482_c2_113_020713
Description
UG482 (v1.9) December 19, 2016