Xilinx 7 Series User Manual page 101

Figure 3-14
X-Ref Target - Figure 3-14
Slave
GTP TX
Lane 3
Master
GTP TX
Lane 2
Slave
GTP TX
Lane 1
Slave
GTP TX
Lane 0
Figure 3-14: TX Buffer Bypass in Multi-Lane Mode Example
These GTP transceiver settings are used to bypass the TX buffer:
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•
•
With the GTP transceiver reference clock selected, TXOUTCLK is used as the source of the
TXUSRCLK. The user must ensure that TXOUTCLK and the selected GTP transceiver reference
clock is running and operating at the desired frequency. When the TX buffer is bypassed, the TX
phase alignment procedure must be performed after these events:
•
•
•
•
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows an example of buffer bypass master versus slave lanes.
TXUSRCLK
TXUSRCLK2
TXOUTCLK
BUFG
TXUSRCLK
TXUSRCLK2
TXUSRCLK
TXUSRCLK2
TXUSRCLK
TXUSRCLK2
TXBUF_EN = FALSE
TX_XCLK_SEL = TXUSR
TXOUTCLKSEL = 3'b011 or 3'b100 to select the GTP transceiver reference clock as the
source of TXOUTCLK
Resetting or powering up the GTP transceiver transmitter
Resetting or powering up the PLL
Change of the GTP transceiver reference clock source or frequency
Change of the TX line rate
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MMCM / PLL
BUFG
UG482_c3_115_020413
TX Buffer Bypass
101
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