Running Disparity - Xilinx 7 Series User Manual

Chapter 3: Transmitter
X-Ref Target - Figure 3-6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
TXDATA H3 G3 F3 E3 D3 C3 B3 A3 H2 G2 F2 E2 D2 C2 B2 A2 H1 G1 F1 E1 D1 C1 B1 A1 H0 G0 F0 E0 D0 C0 B0 A0
j3 h3 g3 f3 i3 e3 d3 c3 b3 a3 j2 h2 g2 f2 i2 e2 d2 c2 b2 a2 j1 h1 g1 f1 i1 e1 d1 c1 b1 a1 j0 h0 g0 f0 i0 e0 d0 c0 b0 a0
Transmitted
Last

Running Disparity

8B/10B coding is DC-balanced, meaning that the long-term ratio of 1s and 0s transmitted should be
exactly 50%. To achieve this, the encoder always calculates the difference between the number of 1s
transmitted and the number of 0s transmitted, and at the end of each character transmitted, makes the
difference either +1 or –1. This difference is known as the running disparity.
To accommodate protocols that use disparity to send control information, the running disparity not
only can be generated by the 8B/10B encoder but is also controllable through
TXCHARDISPMODE and TXCHARDISPVAL as shown in
character sent with reversed disparity might be used to trigger clock correction.
Table 3-6: TXCHARDISPMODE and TXCHARDISPVAL versus Outgoing Disparity
TXCHARDISPMODE TXCHARDISPVAL
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TX_DATA_WIDTH = 20
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA H1 G1 F1 E1 D1 C1 B1 A1 H0 G0 F0 E0 D0 C0 B0 A0
MSB
j1 h1 g1 f1 i1 e1 d1 c1 b1 a1 j0 h0 g0 f0 i0 e0 d0 c0 b0 a0
Transmitted
Last
TX_DATA_WIDTH = 40
Figure 3-6: 8B/10B Bit and Byte Ordering
0
0
1
1
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8B/10B
Transmitted
7 6 5 4 3 2 1 0
8B/10B
0 Calculated by the 8B/10B encoder.
1 Inverts running disparity when encoding TXDATA.
Forces running disparity negative when encoding
0
TXDATA.
Forces running disparity positive when encoding
1
TXDATA.
7 Series FPGAs GTP Transceivers User Guide
LSB
First
MSB
Transmitted
UG482_c3_06_110911
Table 3-6. For example, an Idle
Outgoing Disparity
UG482 (v1.9) December 19, 2016
LSB
First